Fixes for sdhci-bcm2708

possible fix for sdcard missing status. Thank naren

sdcard patch improvements from naren

sdhci-bcm2708: speed up DMA sync

Experiments show that it doesn't really take that long to sync, so we
can reduce the poll interval slightly. Might improve performance a bit.

sdhci-bcm2708: remove custom clock handling

The custom clock handling code is redundant and buggy. The MMC/SDHCI
subsystem does a better job than it, so remove it for good.

sdhci-bcm2708: add additional quirks

Some additional quirks are needed for correct operation.
There's no SDHCI capabilities register documented, and it always reads
zero, so add SDHCI_QUIRK_MISSING_CAPS. Apparently
SDHCI_QUIRK_NO_HISPD_BIT is needed for many cards to work correctly in
high-speed mode, so add it as well.

sdhci-bcm2708: add allow_highspeed parameter

Add a parameter to disable high-speed mode for the few cards that
still might have problems. High-speed mode is enabled by default.

sdhci-bcm2708: assume 50 MHz eMMC clock

80 MHz clock isnt't suited well to be dividable to get SD clocks of 25
MHz (default mode) or 50 MHz (high speed mode). 50 MHz are perfect to
drive the SD interface at ideal frequencies.

Allow emmc clock to be specified as command line parameter

sdhci-bcm2708: raise DMA sync timeout

Commit d64b84ca by accident reduced the maximum overall DMA sync
timeout. The maximum overall timeout was reduced from 100ms to 30ms,
which isn't enough for many cards. Increase it to 150ms, just to be
extra safe. According to commit 872a8ff7 in the MMC subsystem, some
cards require crazy long timeouts (3s), but as we're busy-waiting,
and shouldn't delay for such a long time, let's hope 150ms will be
enough for most cards.

Use ndelay rather than udelay. Thanks lb

Add sync_after_dma module parameter

sdhci-bcm2708: use extension FIFO to buffer DMA transfers

The additional FIFO might speed up transfers in some cases.

sdhci-bcm2708: use multiblock-type transfers for single blocks

There are issues with both single block reads (missed completion)
and writes (data loss in some cases!). Just don't do single block
transfers anymore, and treat them like multiblock transfers. This
adds a quirk for this and uses it.

Add module parameter for missing_status quirk. sdhci-bcm2708.missing_status=0 may improve interrupt latency

Fix spinlock recursion in sdhci-bcm2708.c

mmc: Report 3.3V support in caps

sdhci: Use macros for out spin lock/unlock functions to reduce diffs with upstream code

sdhci: sdhci_bcm2708_quirk_voltage_broken appears to be a no-op

sdhci: sdhci_bcm2708_uhs_broken should be handled through caps reported

Add low-latency mode to sdcard driver. Disable with sdhci-bcm2708.enable_llm=0. Thanks ddv2005.

Allow the number of cycles delay between sdcard peripheral writes to be specified on command line with sdhci-bcm2708.cycle_delay

Lazy CRC quirk: Implemented retrying mechanisms for SD SSR and SCR, disabled missing_status and spurious CRC ACMD51 quirks by default (should be fixed by the retrying-mechanishm)

mmc: suppress sdcard warnings we are happy about by default

sdhci-bcm2807: Increase sync_after_dma timeout

The current timeout is being hit with some cards that complete successfully with a longer timeout.
The timeout is not handled well, and is believed to be a code path that causes corruption.
872a8ff7 suggests that crappy cards can take up to 3 seconds to respond

remove suspend/resume

fix sign in sdhci_bcm2708_raw_writel wait calculation

The ns_wait variable is intended to hold a lower bound on the number of nanoseconds that have elapsed since the last sdhci register write. However, the actual calculation of it was incorrect, as the subtraction was inverted. This commit fixes the calculation.

Note that this correction has no bearing when running with the default cycle_delay of 2 and the default clock rate of 50 MHz, under which conditions ns_2clk is 40 nanoseconds and ns_wait, regardless of whether the subtraction is done correctly or incorrectly, cannot possibly be less than 40 except for during the one-microsecond period just before the tick counter wraps around to meet last_write_hpt (i.e., approximately 4295 seconds after the preceding sdhci register write). The correction in this commit only comes into play if ns_2clk > 1000, which requires a cycle_delay of 51 or greater when using the default clock rate. Under those conditions, sdhci_bcm2708_raw_writel will not wait for the full cycle_delay count if at least 1000 nanoseconds have elapsed since the last register write.

sdhci: Only do one iteration of PIO reading loop

Changed wording on logging. Previously, we received errors like this:
mmc0: could read SD Status register (SSR) at the 3th attempt
A more sensible response is now returned.
A typo also fixed in comments.