ASoC: pcm512x: implement set_tdm_slot interface

PCM512x can accept data padded with additional BCLK cycles
but the driver currently lacks an interface to configure this.

This leads to the problem that S24_LE format in master mode
can result in non-integer clock divisors and pcm512x running
at a rather off rate.

For example 48kHz with 48fs BCLK and SCLK at 24.576MHz uses
a divisor of 10 (rounded down from 10.6666) and results in a
51.2kHz LRCLK. With 64fs BCLK a divisor of 8 is used and
LRCLK runs at exactly 48kHz.

Fix this by providing a minimal set_tdm_slot implementation
so machine drivers can optionally configure custom BCLK ratios.

Signed-off-by: Matthias Reichl <hias@horus.com>