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Commit c3480a60 authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
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bnxt_en: Add cache line size setting to optimize performance.



The chip supports 64-byte and 128-byte cache line size for more optimal
DMA performance when matched to the CPU cache line size.  The default is 64.
If the system is using 128-byte cache line size, set it to 128.

Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 91cdda40
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