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Commit c04bf559 authored by Thierry Reding's avatar Thierry Reding Committed by Peter De Schrijver
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clk: tegra: Properly setup PWM clock on Tegra30 



The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.

Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 43e36a96
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