Commit b61f1daf authored by Grigori Goronzy's avatar Grigori Goronzy Committed by popcornmix
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sdhci-bcm2708: assume 50 MHz eMMC clock

80 MHz clock isnt't suited well to be dividable to get SD clocks of 25
MHz (default mode) or 50 MHz (high speed mode). 50 MHz are perfect to
drive the SD interface at ideal frequencies.
parent 66be34f3
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