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Commit 45a284bc authored by Will Deacon's avatar Will Deacon Committed by Catalin Marinas
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arm64: tlb: Add DSB ISHST prior to TLBI in __flush_tlb_[kernel_]pgtable()



__flush_tlb_[kernel_]pgtable() rely on set_pXd() having a DSB after
writing the new table entry and therefore avoid the barrier prior to the
TLBI instruction.

In preparation for delaying our walk-cache invalidation on the unmap()
path, move the DSB into the TLB invalidation routines.

Acked-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent 6899a4c8
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