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Commit 3e37b005 authored by Chunyan Zhang's avatar Chunyan Zhang Committed by Stephen Boyd
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clk: sprd: add adjustable pll support



Introduced a common adjustable pll clock driver for Spreadtrum SoCs.

Signed-off-by: default avatarChunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 4fcba55c
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