- Aug 10, 2017
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Michael Ellerman authored
Both xive_core_init() and xive_native_init() are called from and call __init routines, so they should also be __init. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
early_check_vec5() is called from and calls __init routines, so should also be __init. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
head_8xx is dedicated to 8xx so no need to use macros that depends on the CPU Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
Use symbolic names for DSISR bits in DSI Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
For the 8xx, PVR values defined in arch/powerpc/include/asm/reg.h are nowhere used. Remove all defines and add PVR_8xx Use it in arch/powerpc/kernel/cputable.c Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx arch/powerpc/platforms/Kconfig.cputype has contained the following comment about CONFIG_8xx item for some years: "# this is temp to handle compat with arch=ppc" There is no more users of CONFIG_8xx, so remove it. Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
Two config options exist to define powerpc MPC8xx: * CONFIG_PPC_8xx * CONFIG_8xx arch/powerpc/platforms/Kconfig.cputype has contained the following comment about CONFIG_8xx item for some years: "# this is temp to handle compat with arch=ppc" arch/powerpc is now the only place with remaining use of CONFIG_8xx: get rid of them. Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
4xx, CPM2 and 8xx cannot be selected at the same time, so no need to test 8xx && !4xx && !CPM2. Testing 8xx is enough. Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
The 8xx cannot access the TBL and TBU registers using mfspr/mtspr It must be accessed using mftb/mftbu Due to this, there is a number of places with #ifdef CONFIG_8xx This patch defines new macros MFTBL(x) and MFTBU(x) on the same model as MFTB(x) and tries to make use of them as much as possible. In arch/powerpc/include/asm/timex.h, we also remove the ifdef for the asm() operands as the compiler doesn't mind unused operands Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
mpc8xx_pic.c is dedicated to the 8xx, so move it to platform/8xx Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
To remain consistent with what is done with CPM2, let's link CPM1 related parts to CONFIG_CPM1 instead of CONFIG_8xx When something depends on both CPM1 and CPM2 we associate it with CONFIG_CPM Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
Since commit aa42c69c ("[POWERPC] Add support for FP emulation for the e300c2 core"), program_check_exception() can be called for math emulation. In that case, 'reason' is 0. On the 8xx, there is a Software Emulation interrupt which is called for all unimplemented and illegal instructions. This interrupt calls SoftwareEmulation() which does almost the same as program_check_exception() called with reason = 0. The Software Emulation interrupt sets all reason bits to 0, it is therefore possible to call program_check_exception() directly from the interrupt handler. Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
In the same spirit as what was done for 4xx and 44x, move the 8xx machine check into platforms/8xx Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Christophe Leroy authored
The entire 8xx directory is omitted if CONFIG_8xx is not enabled, so within the 8xx/Makefile CONFIG_8xx is always y. So convert obj-$(CONFIG_8xx) to the more obvious obj-y. Signed-off-by:
Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
Currently we open code the reason codes for program checks. Instead use the existing SRR1 defines. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
We already have mce.c which is built for 64bit and contains other parts of the machine check code, so move these bits in there too. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
Make it clear that the fallback version of machine_check_generic() is only used on 32-bit configs. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
get_mc_reason() no longer provides (if it ever really did) any meaningful abstraction, so remove it. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
Now that we have 4xx platform directory we can move the 4xx machine check handler in there. Again we drop get_mc_reason() and replace it with regs->dsisr directly (which is actually SPRN_ESR). Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
We have a lot of code in sysdev for supporting 4xx, ie. either 40x or 44x. Instead it would be cleaner if it was all in platforms/4xx. This is slightly odd in that we don't actually define any machines in the 4xx platform, as is usual for a platform directory. But still it seems like a better result to have all this related code in a directory by itself. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
We have several 44x machine check handlers defined in traps.c. It would be preferable if they were split out with the platforms that use them. Do that. In the process, drop get_mc_reason() and instead just open code the lookup of reason from regs->dsisr. This avoids a pointless layer of abstraction. We know to use regs->dsisr because 44x enables BOOKE which enables PPC_ADV_DEBUG_REGS, and FSL_BOOKE is not enabled on 44x builds. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
The entire 44x directory is omitted if CONFIG_44x is not enabled, so within the 44x/Makefile CONFIG_44x is always y. So convert obj-$(CONFIG_44x) to the more obvious obj-y. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Michael Ellerman authored
Currently we build the 47x cputable entries even when CONFIG_PPC_47x is disabled. That means a kernel built without CONFIG_PPC_47x will claim to support a 47x CPU and start booting, only to break somewhere later because it doesn't have 47x support compiled in. So guard the 47x cputable entries with CONFIG_PPC_47x. Note that this is inside the #ifdef CONFIG_44x section, because 47x depends on 44x. Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Shilpasri G Bhat authored
Adds support for clearing different sensor groups. OCC inband sensor groups like CSM, Profiler, Job Scheduler can be cleared using this driver. The min/max of all sensors belonging to these sensor groups will be cleared. Signed-off-by:
Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Shilpasri G Bhat authored
This patch adds support to set power-shifting-ratio which hints the firmware how to distribute/throttle power between different entities in a system (e.g CPU v/s GPU). This ratio is used by OCC for power capping algorithm. Signed-off-by:
Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Shilpasri G Bhat authored
Adds a generic powercap framework to change the system powercap inband through OPAL-OCC command/response interface. Signed-off-by:
Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Nicholas Piggin authored
This driver currently reports the H_BEST_ENERGY hypervisor call is unsupported (even when booting in a non-virtualised environment). This is not something the administrator can do much with, and not significant for debugging. Remove it. Signed-off-by:
Nicholas Piggin <npiggin@gmail.com> Reviewed-by:
Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Matt Brown authored
This adds emulation for the isel instruction. Tested for correctness against the isel instruction and its extended mnemonics (lt, gt, eq) on ppc64le. Signed-off-by:
Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by:
Cyril Bur <cyrilbur@gmail.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Matt Brown authored
This adds emulation for the prtyw and prtyd instructions. Tested for logical correctness against the prtyw and prtyd instructions on ppc64le. Signed-off-by:
Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by:
Cyril Bur <cyrilbur@gmail.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Matt Brown authored
This adds emulation for the bpermd instruction. Tested for correctness against the bpermd instruction on ppc64le. Signed-off-by:
Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by:
Cyril Bur <cyrilbur@gmail.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Matt Brown authored
This adds emulations for the popcntb, popcntw, and popcntd instructions. Tested for correctness against the popcnt{b,w,d} instructions on ppc64le. Signed-off-by:
Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by:
Cyril Bur <cyrilbur@gmail.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Matt Brown authored
This patch adds emulation of the cmpb instruction, enabling xmon to emulate this instruction. Tested for correctness against the cmpb asm instruction on ppc64le. Signed-off-by:
Matt Brown <matthew.brown.dev@gmail.com> Reviewed-by:
Cyril Bur <cyrilbur@gmail.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Madhavan Srinivasan authored
Fixes: 34922527 ("powerpc/perf: Add power9 event list macros for generic and cache events") Signed-off-by:
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Madhavan Srinivasan authored
Add couple of more events (PM_LD_MISS_L1 and PM_BR_2PATH) to power9 event list and power9_event_alternatives array (these events can be counted in more than one PMC). Signed-off-by:
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Madhavan Srinivasan authored
There are some hardware events on Power systems which only count when the processor is not idle, and there are some fixed-function counters which count such events. For example, the "run cycles" event counts cycles when the processor is not idle. If the user asks to count cycles, we can use "run cycles" if this is a per-task event, since the processor is running when the task is running, by definition. We can't use "run cycles" if the user asks for "cycles" on a system-wide counter. Currently in power8 this check is done using PPMU_ONLY_COUNT_RUN flag in power8_get_alternatives() function. Based on the flag, events are switched if needed. This function should also be enabled in power9, so factor out the code to isa207_get_alternatives(). Fixes: efe881af ('powerpc/perf: Factor out event_alternative function') Reported-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Madhavan Srinivasan authored
Commit 20dd4c62 ('powerpc/perf: Fix SDAR_MODE value for continous sampling on Power9') set the default sdar_mode value in MMCRA[SDAR_MODE] to be used as 0b01 (Update on TLB miss). And this value is set if sdar_mode from event is zero, or we are in continous sampling mode in power9 dd1. But it is preferred to have the sdar_mode value for power9 as 0b10 (Update on dcache miss) for better sampling updates instead of 0b01 (Update on TLB miss). From Anton: Using a bandwidth test case with a 1MB footprint, I profiled cycles and chose TLB updates of the SDAR: $ perf record -d -e r000400000000001E:u ./bw2001 1M ^ SDAR TLB $ perf report -D | grep PERF_RECORD_SAMPLE | sed 's/.*addr: //' | sort -u | wc -l 4 I get 4 unique addresses. If I ran with dcache misses: $ perf record -d -e r000800000000001E:u ./bw2001 1M ^ SDAR dcache miss $ perf report -D|grep PERF_RECORD_SAMPLE| sed 's/.*addr: //'|sort -u | wc -l 5217 I get 5217 unique addresses. No surprises here, but it does show why TLB misses is the wrong event to default to - we get very little useful information out of it. Signed-off-by:
Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Acked-by:
Anton Blanchard <anton@samba.org> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Ivan Mikhaylov authored
Add mmc0 changes for enabling arasan emmc and change defconfig appropriately. Signed-off-by:
Ivan Mikhaylov <ivan@de.ibm.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Suraj Jitindar Singh authored
The host process table base is stored in the partition table by calling the function native_register_process_table(). Currently this just sets the entry in memory and is missing a subsequent cache invalidation instruction. Any update to the partition table should be followed by a cache invalidation instruction specifying invalidation of the caching of any partition table entries (RIC = 2, PRS = 0). We already have a function to update the partition table with the required cache invalidation instructions - mmu_partition_table_set_entry(). Update the native_register_process_table() function to call mmu_partition_table_set_entry(), this ensures all appropriate invalidation will be performed. Signed-off-by:
Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by:
Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> [mpe: Use a local for patb0 to clean it up slightly] Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Benjamin Herrenschmidt authored
Ensure irqd is active before attempting to set affinity. This should make the set affinity code more robust. For instance, this prevents these messages seen on a 4.12 based kernel when taking cpus offline: [ 123.053037264,3] XIVE[ IC 00 ] ISN 2 lead to invalid IVE ! [ 77.885859] xive: Error -6 reconfiguring irq 17 [ 77.885862] IRQ17: set affinity failed(-6). That particular case has been fixed in 4.13-rc1 by commit 91f26cb4 ("genirq/cpuhotplug: Do not migrated shutdown irqs"). Signed-off-by:
Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> Signed-off-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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Nicholas Piggin authored
This adds an irq counter for the watchdog soft-NMI. This interrupt only fires when interrupts are soft-disabled, so it will not increment much even when the watchdog is running. However it's useful for debugging and sanity checking. Signed-off-by:
Nicholas Piggin <npiggin@gmail.com> Signed-off-by:
Michael Ellerman <mpe@ellerman.id.au>
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