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  1. May 31, 2014
    • Paul Burton's avatar
      MIPS: Malta: Let PIIX4 respond to PCI special cycles · 9e53481e
      Paul Burton authored 
      

This patch enables the PIIX4 to respond to special cycles on the PCI
bus. One such special cycle must be used in order to enter a suspend
state, and if response to it is not enabled then the suspend state will
never be entered.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6904/
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      9e53481e
    • Paul Burton's avatar
      MIPS: Malta: add suspend state entry code · b6911bba
      Paul Burton authored 
      

This patch introduces code which will enter a suspend state via the
PIIX4. This can only be done when PCI support is enabled since it
requires access to PCI I/O space and the generation of a special cycle
on the PCI bus. In cases where PCI is disabled the mips_pm_suspend
function will simply always return an error.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6905/
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      b6911bba
    • Paul Burton's avatar
      MIPS: Define some more PIIX4 registers & values · 643c5705
      Paul Burton authored 
      

This patch simply adds definitions for some I/O registers in the PIIX4
PM device, and the magic data for a special cycle which must occur on
the PCI bus in order for the PIIX4 to enter a suspend state.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6903/
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      643c5705
    • Maciej W. Rozycki's avatar
      MIPS: DEC: Remove the Halt button interrupt on R4k systems · 76ad023b
      Maciej W. Rozycki authored 
      

On R4k DECstations the Halt button is wired to the NMI processor input
rather than an ordinary interrupt input such as on R3k DECstations.  This
is possible with a different design of the CPU daughtercard that routes
the Halt button line from the baseboard connector.  Additionally the
interrupt input has been reused for a different purpose on the KN04 and
KN05 R4k CPU daughtercards so it is better kept masked.

Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6705/
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      76ad023b
    • Maciej W. Rozycki's avatar
      MIPS: DEC: Only select the R4k clock event/source on R4k systems · 81d10bad
      Maciej W. Rozycki authored 
      

R3k systems have no R4k timer so there's no point in pulling code that's
going to be dead.

Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6704/
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      81d10bad
    • Maciej W. Rozycki's avatar
      MIPS: __delay ABI-dependent subtraction simplification · e496453d
      Maciej W. Rozycki authored 
      

This small update to the previous fix to __delay removes a conditional
around the ABI-dependent subtraction operation within an inline asm in
favor to the standard <asm/asm.h> LONG_SUBU macro.  No change in code
produced.

Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6703/
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      e496453d
    • Maciej W. Rozycki's avatar
      MIPS: Implement random_get_entropy with CP0 Random · 06947aaa
      Maciej W. Rozycki authored 
      Update to commit 9c9b415c

 [MIPS:
Reimplement get_cycles().]

On systems were for whatever reasons we can't use the cycle counter, fall
back to the c0_random register as an entropy source.  It has however a
very small range that makes it suitable for random_get_entropy only and
not get_cycles.

This optimised version compiles to 8 instructions in the fast path even in
the worst case of all the conditions to check being variable (including a
MFC0 move delay slot that is only required for very old processors):

     828:	8cf90000 	lw	t9,0(a3)
			828: R_MIPS_LO16	jiffies
     82c:	40057800 	mfc0	a1,c0_prid
     830:	3c0200ff 	lui	v0,0xff
     834:	00a21024 	and	v0,a1,v0
     838:	1040007d 	beqz	v0,a30 <add_interrupt_randomness+0x22c>
     83c:	3c030000 	lui	v1,0x0
			83c: R_MIPS_HI16	cpu_data
     840:	40024800 	mfc0	v0,c0_count
     844:	00000000 	nop
     848:	00409021 	move	s2,v0
     84c:	8ce20000 	lw	v0,0(a3)
			84c: R_MIPS_LO16	jiffies

On most targets the sequence will be shorter and on some it will reduce to
a single `MFC0 <reg>,c0_count', as all MIPS architecture (i.e. non-legacy
MIPS) processors require the CP0 Count register to be present.

The only known exception that reports MIPS architecture compliance, but
contrary to that lacks CP0 Count is the Ingenic JZ4740 thingy.  For broken
platforms like that this code requires cpu_has_counter to be hardcoded to
0 (i.e. no variable setting is permitted) so as not to penalise all the
other good platforms out there.

The asm barrier is required so that the compiler does not pull any
potentially costly (cold cache!) `cpu_data' variable access into the fast
path.

Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
Signed-off-by: default avatarMaciej W. Rozycki <macro@linux-mips.org>
Cc: Theodore Ts'o <tytso@mit.edu>
Cc: John Crispin <blogic@openwrt.org>
Cc: Andrew McGregor <andrewmcgr@gmail.com>
Cc: Dave Taht <dave.taht@bufferbloat.net>
Cc: Felix Fietkau <nbd@nbd.name>
Cc: Simon Kelley <simon@thekelleys.org.uk>
Cc: Jim Gettys <jg@freedesktop.org>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6702/
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      06947aaa
  3. May 30, 2014