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  1. Jan 11, 2009
    • David Daney's avatar
      MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon. · 5b3b1688
      David Daney authored
      
      
      These are the rest of the new files needed to add OCTEON processor
      support to the Linux kernel.  Other than Makefile and Kconfig which
      should be obvious, we have:
      
      csrc-octeon.c   -- Clock source driver for OCTEON.
      dma-octeon.c    -- Helper functions for mapping DMA memory.
      flash_setup.c   -- Register on-board flash with the MTD subsystem.
      octeon-irq.c    -- OCTEON interrupt controller managment.
      octeon-memcpy.S -- Optimized memcpy() implementation.
      serial.c        -- Register 8250 platform driver and early console.
      setup.c         -- Early architecture initialization.
      smp.c           -- OCTEON SMP support.
      octeon_switch.S -- Scheduler context switch for OCTEON.
      c-octeon.c      -- OCTEON cache controller support.
      cex-oct.S       -- OCTEON cache exception handler.
      
      asm/mach-cavium-octeon/*.h -- Architecture include files.
      
      Signed-off-by: default avatarTomaso Paoletti <tpaoletti@caviumnetworks.com>
      Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      
       create mode 100644 arch/mips/cavium-octeon/Kconfig
       create mode 100644 arch/mips/cavium-octeon/Makefile
       create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c
       create mode 100644 arch/mips/cavium-octeon/dma-octeon.c
       create mode 100644 arch/mips/cavium-octeon/flash_setup.c
       create mode 100644 arch/mips/cavium-octeon/octeon-irq.c
       create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S
       create mode 100644 arch/mips/cavium-octeon/serial.c
       create mode 100644 arch/mips/cavium-octeon/setup.c
       create mode 100644 arch/mips/cavium-octeon/smp.c
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
       create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h
       create mode 100644 arch/mips/include/asm/octeon/octeon.h
       create mode 100644 arch/mips/kernel/octeon_switch.S
       create mode 100644 arch/mips/mm/c-octeon.c
       create mode 100644 arch/mips/mm/cex-oct.S
      5b3b1688
    • David Daney's avatar
      MIPS: Add Cavium OCTEON processor support files to... · 58f07778
      David Daney authored
      
      MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon/executive and asm/octeon.
      
      These files are used to coordinate resource sharing between all of
      the programs running on the OCTEON SOC.  The OCTEON processor has many
      CPU cores (current parts have up to 16, but more are possible).  It
      also has a variety of on-chip hardware blocks for things like network
      acceleration, encryption and RAID.
      
      One typical configuration is to run Linux on several of the CPU cores,
      and other dedicated applications on the other cores.
      
      Resource allocation between the various programs running on the system
      (Linux kernel and other dedicated applications) needs to be
      coordinated.  The code we use to do this we call the 'executive'.  All
      of this resource allocation and sharing code is gathered together in
      the executive directory.
      
      Included in the patch set are the following files:
      
      cvmx-bootmem.c and cvmx-sysinfo.c -- Coordinate memory allocation.
      All memory used by the Linux kernel is obtained here at boot time.
      
      cvmx-l2c.c -- Coordinates operations on the shared level 2 cache.
      
      octeon-model.c  -- Probes chip capabilities and version.
      
      The corresponding headers are in asm/octeon.
      
      Signed-off-by: default avatarTomaso Paoletti <tpaoletti@caviumnetworks.com>
      Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      
       create mode 100644 arch/mips/cavium-octeon/executive/Makefile
       create mode 100644 arch/mips/cavium-octeon/executive/cvmx-bootmem.c
       create mode 100644 arch/mips/cavium-octeon/executive/cvmx-l2c.c
       create mode 100644 arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
       create mode 100644 arch/mips/cavium-octeon/executive/octeon-model.c
       create mode 100644 arch/mips/include/asm/octeon/cvmx-asm.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-bootinfo.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-bootmem.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-l2c.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-packet.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-spinlock.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx-sysinfo.h
       create mode 100644 arch/mips/include/asm/octeon/cvmx.h
       create mode 100644 arch/mips/include/asm/octeon/octeon-feature.h
       create mode 100644 arch/mips/include/asm/octeon/octeon-model.h
      58f07778
    • David Daney's avatar
      MIPS: Add Cavium OCTEON processor CSR definitions · 54293ec3
      David Daney authored
      
      
      Here we define the addresses and bit-fields of the Configuration and
      Status Registers (CSRs) for some of the hardware functional units on
      the OCTEON SOC.
      
      Definitions are needed for:
      
      CIU  -- Central Interrupt Unit.
      GPIO -- General Purpose Input Output.
      IOB  -- Input / Output {Busing,Bridge}.
      IPD  -- Input Packet Data unit.
      L2C  -- Level-2 Cache controller.
      L2D  -- Level-2 Data cache.
      L2T  -- Level-2 cache Tag.
      LED  -- Light Emitting Diode controller.
      MIO  -- Miscellaneous Input / Output.
      POW  -- Packet Order / Work unit.
      
      Signed-off-by: default avatarTomaso Paoletti <tpaoletti@caviumnetworks.com>
      Signed-off-by: default avatarDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      54293ec3
    • Julia Lawall's avatar
      MIPS: Alchemy: Change strict_strtol to strict_strtoul · 2bd2dd05
      Julia Lawall authored
      Since memsize is unsigned, it would seem better to use strict_strtoul that
      strict_strtol.
      
      A simplified version of the semantic patch that makes this change is as
      follows: (http://www.emn.fr/x-info/coccinelle/
      
      )
      
      // <smpl>
      @s2@
      long e;
      position p;
      @@
      
      strict_strtol@p(...,&e)
      
      @@
      position p != s2.p;
      type T;
      T e;
      @@
      
      - strict_strtol@p
      + strict_strtoul
        (...,&e)
      // </smpl>
      
      Signed-off-by: default avatarJulia Lawall <julia@diku.dk>
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      2bd2dd05
    • Anirban Sinha's avatar
    • Linus Torvalds's avatar
      Linux 2.6.29-rc1 · c5976504
      Linus Torvalds authored
      v2.6.29-rc1
      c5976504
    • Arjan van de Ven's avatar
      bootgraph: make the bootgraph script show async waiting time · d3f8ddea
      Arjan van de Ven authored
      
      
      It is useful for diagnosing boot performance to see where async function
      calls are waiting on serialization...  this patch adds this
      functionality to the bootgraph.pl script.
      
      The waiting time is shown as a half transparent, gray bar through the
      block that is waiting.
      
      Signed-off-by: default avatarArjan van de Ven <arjan@linux.intel.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      d3f8ddea
    • Arjan van de Ven's avatar
      libata: only ports >= 0 need to synchronize · fa853a48
      Arjan van de Ven authored
      
      
      In a discussio with Jeff Garzik, he mentioned that the serialization
      for the libata port probes only needs to be within the domain of a host.
      This means that for the first port of each host (with ID 0), we don't
      need to wait, so we can relax our serialization a little.
      
      Signed-off-by: default avatarArjan van de Ven <arjan@linux.intel.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      fa853a48
    • Arjan van de Ven's avatar
      libata: Add a per-host flag to opt-in into parallel port probes · 886ad09f
      Arjan van de Ven authored
      
      
      This patch adds a per host flag that allows drivers to opt in into
      having its busses scanned in parallel.
      
      Drivers that do not set this flag get their ports scanned in
      the "original" sequence.
      
      Signed-off-by: default avatarArjan van de Ven <arjan@linux.intel.com>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      886ad09f
  2. Jan 10, 2009