- Mar 27, 2014
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Paul Burton authored
When saving or restoring scalar FP context we want to access the least significant 64 bits of each FP register. When the FP registers are 64 bits wide that is trivially the start of the registers value in memory. However when the FP registers are wider this equivalence will no longer be true for big endian systems. Define a new set of offset macros for the least significant 64 bits of each saved FP register within thread context, and make use of them when saving and restoring scalar FP context. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6428/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
When we want to access 64-bit FP register values we can only treat consecutive registers as being consecutive in memory when the width of an FP register equals 64 bits. This assumption will not remain true once MSA support is introduced, so provide a code path which copies each 64 bit FP register value in turn when the width of an FP register differs from 64 bits. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6427/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
This code assumed that saved FP registers are 64 bits wide, an assumption which will no longer be true once MSA is introduced. This patch modifies the code to copy the lower 64 bits of each register in turn, which is safe for any FP register width >= 64 bits. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6425/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The upper bits of an FP register are architecturally defined as unpredictable following an instructions which only writes the lower bits. The prior behaviour of the kernel is to leave them unmodified. This patch modifies that to clear the upper bits to zero. This is what the MSA architecture reference manual specifies should happen for its wider registers and is still permissible for scalar FP instructions given the bits unpredictability there. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: sergei.shtylyov@cogentembedded.com Patchwork: https://patchwork.linux-mips.org/patch/6435/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
NUM_FPU_REGS just makes it clearer what's going on, rather than the magic hard coded 32. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6424/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
When a task which has used the FPU at some point in its past takes a signal the kernel would previously always require the task to take ownership of the FPU whilst setting up or restoring from the sigcontext. That means that if the task has not used the FPU within this timeslice then the kernel would enable the FPU, restore the task's FP context into FPU registers and then save them into the sigcontext. This seems inefficient, and if the signal handler doesn't use FP then enabling the FPU & the extra memory accesses are entirely wasted work. This patch modifies the sigcontext setup & restore code to copy directly between the tasks saved FP context & the sigcontext for any tasks which have used FP in the past but are not currently the FPU owner (ie. have not used FP in this timeslice). Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6423/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
These functions aren't directly related to the FPU emulator at all, they simply copy between a thread's saved context & a sigcontext. Thus move them to the appropriate signal files & rename them accordingly. This makes it clearer that the functions don't require the FPU emulator in any way. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6422/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The hard-coded offsets mentioned in this comment seem to not exist anymore, so remove mention of them from the comment. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6421/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
This patch replaces the fpureg_t typedef with a "union fpureg" enabling easier access to 32 & 64 bit values. This allows the access macros used in cp1emu.c to be simplified somewhat. It will also make it easier to expand the width of the FP registers as will be done in a future patch in order to support the 128 bit registers introduced with MSA. No behavioural change is intended by this patch. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
Qais Yousef <qais.yousef@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6532/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6401/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
When userland uses syscall() to perform an indirect system call the actually system call that needs to be checked by the filter is on the first argument. The kernel code needs to handle this case by looking at the original syscall number in v0 and if it's NR_syscall, then it needs to examine the first argument to identify the real system call that will be executed. Similarly, we need to 'virtually' shift the syscall() arguments so the syscall_get_arguments() function can fetch the correct arguments for the indirect system call. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6404/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6399/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
MIPS now has the infrastructure for dynamic seccomp-bpf filtering Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6400/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
Add _TIF_SECCOMP flag to _TIF_WORK_SYSCALL_ENTRY to indicate that the system call needs to be checked against a seccomp filter. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6405/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
This effectively renames __syscall_get_arch to syscall_get_arch and implements a compatible interface for the seccomp API. The seccomp code (kernel/seccomp.c) expects a syscall_get_arch function to be defined for every architecture, so we drop the leading underscores from the existing function. This also makes use of the 'task' argument to determine the type the process instead of assuming the process has the same characteristics as the kernel it's running on. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6398/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
The syscall_rollback function is used by seccomp-bpf but it was never added for MIPS. It doesn't need to do anything as none of the registers are clobbered if the system call has been denied by the seccomp filter. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Reviewed-by:
James Hogan <james.hogan@imgtec.com> Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6403/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
CONFIG_MIPS_CPS is a better option for systems where it is supported, which as far as I am aware should be all systems where CONFIG_MIPS_CMP could provide any value (ie. where there are multiple cores for YAMON to bring up). This option is therefore deprecated, and marked as such. It is left intact for the time being in order to provide a fallback should someone find a system where CONFIG_MIPS_CPS will not function (ie. where the reset vector cannot be moved), and should be removed entirely in the future assuming that does not happen. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6369/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
Commit f55afb0969cc "MIPS: Clean up MIPS MT and CMP configuration options." introduced a dependency upon MIPS_MT_SMP (ie. SMVP) for the MIPS_CMP (ie. CMP framework support) Kconfig option. It did not specify why, and that dependency is bogus. It is perfectly valid to have a multi-core system with the YAMON bootloader but without MT support - an example of this would be any multi-core proAptiv bitstream running on a Malta. Forcing MT support to be enabled in a kernel for such a system is incorrect. I suspect that the dependency was actually meant to reflect the fact that YAMON will only bind 1 TC per VPE on an MT system, and only describe those 1:1 TC:VPE pairs as CPUs through the AMON interface. Thus an SMTC kernel makes little sense on a system using MIPS_CMP, and the Kconfig dependencies should reflect that rather than introducing the bogus SMVP dependency. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6368/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The prior help text introduced in commit f55afb0969cc "MIPS: Clean up MIPS MT and CMP configuration options." reads as though this option enables the kernel to make use of the CM hardware, which is not true. What it actually does is allow the kernel to interact with the YAMON bootloader which actually interacts with the CM hardware to bring up secondary cores. Re-introduce the word "framework" which that commit removed to avoid misleading people. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6367/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
This header was used only by Malta but is used no longer. Remove it. It was also included unnecessarily in irq-gic.c, so that include is also removed. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6366/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
This patch simply attempts to register the MIPS Coherent Processing System SMP implementation when it is enabled. If registering that fails for some reason (like the Kconfig option being disabled or a lack of hardware support) then we fall back to the same SMP implementations as before. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6365/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
When CPC support is compiled into the kernel (ie. CONFIG_MIPS_CPC=y), probe the CPC on boot for Malta in order to allow any users of the CPC to detect its presence & function correctly. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6363/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
Remove the Malta-specific CM probe code and instead make use of the newly added generic CM code. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6364/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The vpe_id field of struct cpuinfo_mips is only present when one of CONFIG_MIPS_MT_{SMP,SMTC} is enabled. That means that any code accessing which may compile without MT is currently forced to use an #ifdef. Instead this patch provides an accessor macro, #ifdef'd appropriately to prevent further #ifdef's elsewhere. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6646/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- Mar 07, 2014
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Paul Burton authored
This patch introduces code to probe for a MIPS Cluster Power Controller & accessor functions to allow for easy register access. This support code will be used by a subsequent patch. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6361/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The kernel currently only probes for a MIPS Coherence Manager in the Malta interrupt code in order to detect & enable the GIC. However CM is not Malta-specific, so this should really be more generic. This patch introduces some non-Malta-specific code which probes for a CM and performs some basic initialisation. A new header, with temporarily duplicated register definitions, is introduced in order to: 1) Allow the new definitions to be correct with regards to the CM documentation, as many of those in gcmpregs.h aren't. 2) Allow switching away from the REG() macro used via a few layers of nested macros in order to access registers in gcmpregs.h. This patch instead introduced accessor functions akin to the {read,write}_c0_* functions used for cop0 registers. 3) Allow users of the CM to be migrated one by one. 4) Switch from the name 'GCMP' to 'CM' since the Coherence Manager is what this code is actually dealing with. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6360/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The GIC IPI functions aren't necessarily specific to the "CMP framework" SMP implementation, and will be used elsewhere in a subsequent commit. This patch adds cleaned up GIC IPI functions to a separate file which is compiled when a new CONFIG_MIPS_GIC_IPI Kconfig symbol is selected, and selects that symbol for CONFIG_MIPS_CMP. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6359/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
This patch adds a simple macro to wrap the ext instruction which was introduced with MIPSR2, and fall back to a shift & and pair for pre-MIPSR2 CPUs. This will be used in a subsequent patch. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6358/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The gic.h header uses bitmaps and NR_CPUS, and should therefore include linux/bitmap.h and linux/threads.h. This is in preparation for use of this header in a subsequent commit from a C file which doesn't already include those headers. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6357/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
The CMGCRBase register is defined by the PRA specification as an optional register which indicates the physical base of the MIPS Coherence Manager Global Control Register block. This patch simply adds a definition for the base address field within the register, along with an accessor function for reading the register. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6356/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Paul Burton authored
These fields will be used from assembly code in a subsequent commit, and defining the size & offset of each field makes that use easier. Signed-off-by:
Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6355/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Steven J. Hill authored
The 1074K is a multiprocessing coherent processing system (CPS) based on modified 74K cores. This patch makes the 1074K an actual unique CPU type, instead of a 74K derivative, which it is not. Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6389/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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Markos Chandras authored
The *Aptiv cores can use the CONF7/IAR bit to detect if the core has hardware support to remove instruction cache aliasing. This also defines the CONF7/AR bit in order to avoid using the '16' magic number. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6499/ Signed-off-by:
Ralf Baechle <ralf@linux-mips.org>
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- Mar 03, 2014
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Linus Torvalds authored
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git://people.freedesktop.org/~airlied/linuxLinus Torvalds authored
Pull drm fixes from Dave Airlie: "Not a huge amount happening, some MAINTAINERS updates, radeon, vmwgfx and tegra fixes" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/vmwgfx: avoid null pointer dereference at failure paths drm/vmwgfx: Make sure backing mobs are cleared when allocated. Update driver date. drm/vmwgfx: Remove some unused surface formats drm/radeon: enable speaker allocation setup on dce3.2 drm/radeon: change audio enable logic drm/radeon: fix audio disable on dce6+ drm/radeon: free uvd ring on unload drm/radeon: disable pll sharing for DP on DCE4.1 drm/radeon: fix missing bo reservation drm/radeon: print the supported atpx function mask MAINTAINERS: update drm git tree entry MAINTAINERS: add entry for drm radeon driver drm/tegra: Add guard to avoid double disable/enable of RGB outputs gpu: host1x: do not check previously handled gathers drm/tegra: fix typo 'CONFIG_TEGRA_DRM_FBDEV'
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usbLinus Torvalds authored
Pull USB fixes from Greg KH: "Here are 2 USB patches for 3.14-rc5, one a new device id, and the other fixes a reported problem with threaded irqs and the USB EHCI driver" * tag 'usb-3.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: usb: ehci: fix deadlock when threadirqs option is used USB: ftdi_sio: add Cressi Leonardo PID
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Linus Torvalds authored
Merge tag 'driver-core-3.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull sysfs fix from Greg KH: "Here is a single sysfs fix for 3.14-rc5. It fixes a reported problem with the namespace code in sysfs" * tag 'driver-core-3.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: sysfs: fix namespace refcnt leak
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git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/stagingLinus Torvalds authored
Pull staging tree fixes from Greg KH: "Here are a few IIO fixes, and a new device id for a staging driver for 3.14-rc5. All have been in linux-next for a while, I did a final merge to get the IIO fixes into this tree, they were incorrectly in the char-misc tree for a few weeks, and I forgot to tell you to pull them from there. This makes it a single pull request for you" * tag 'staging-3.14-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: staging: r8188eu: Add new device ID staging:iio:adc:MXS:LRADC: fix touchscreen statemachine iio:gyro: bug on L3GD20H gyroscope support iio: cm32181: Change cm32181 ambient light sensor driver iio: cm36651: Fix read/write integration time function.
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
more radeon fixes * 'drm-fixes-3.14' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: enable speaker allocation setup on dce3.2 drm/radeon: change audio enable logic drm/radeon: fix audio disable on dce6+ drm/radeon: free uvd ring on unload drm/radeon: disable pll sharing for DP on DCE4.1 drm/radeon: fix missing bo reservation drm/radeon: print the supported atpx function mask
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