Loading Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +3 −2 Original line number Diff line number Diff line Loading @@ -11,7 +11,6 @@ Required properties: - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt - fsl,spi-num-chipselects : Contains the number of the chipselect - cs-gpios : Specifies the gpio pins to be used for chipselects. - clocks : Clock specifiers for both ipg and per clocks. - clock-names : Clock names should include both "ipg" and "per" Loading @@ -21,6 +20,9 @@ See the clock consumer binding, Documentation/devicetree/bindings/dma/dma.txt - dma-names: DMA request names should include "tx" and "rx" if present. Obsolete properties: - fsl,spi-num-chipselects : Contains the number of the chipselect Example: ecspi@70010000 { Loading @@ -29,7 +31,6 @@ ecspi@70010000 { compatible = "fsl,imx51-ecspi"; reg = <0x70010000 0x4000>; interrupts = <36>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */ <&gpio3 25 0>; /* GPIO3_25 */ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; Loading MAINTAINERS +1 −0 Original line number Diff line number Diff line Loading @@ -10799,6 +10799,7 @@ L: linux-spi@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git Q: http://patchwork.kernel.org/project/spi-devel-general/list/ S: Maintained F: Documentation/devicetree/bindings/spi/ F: Documentation/spi/ F: drivers/spi/ F: include/linux/spi/ Loading drivers/spi/spi-imx.c +94 −97 Original line number Diff line number Diff line Loading @@ -59,8 +59,6 @@ struct spi_imx_config { unsigned int speed_hz; unsigned int bpw; unsigned int mode; u8 cs; }; enum spi_imx_devtype { Loading @@ -76,7 +74,7 @@ struct spi_imx_data; struct spi_imx_devtype_data { void (*intctrl)(struct spi_imx_data *, int); int (*config)(struct spi_imx_data *, struct spi_imx_config *); int (*config)(struct spi_device *, struct spi_imx_config *); void (*trigger)(struct spi_imx_data *); int (*rx_available)(struct spi_imx_data *); void (*reset)(struct spi_imx_data *); Loading Loading @@ -112,7 +110,6 @@ struct spi_imx_data { struct completion dma_tx_completion; const struct spi_imx_devtype_data *devtype_data; int chipselect[0]; }; static inline int is_imx27_cspi(struct spi_imx_data *d) Loading Loading @@ -312,7 +309,7 @@ static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); } static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned val = 0; Loading @@ -325,7 +322,7 @@ static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int writel(val, spi_imx->base + MX51_ECSPI_INT); } static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) { u32 reg; Loading @@ -334,9 +331,10 @@ static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MX51_ECSPI_CTRL); } static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, static int mx51_ecspi_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); u32 ctrl = MX51_ECSPI_CTRL_ENABLE; u32 clk = config->speed_hz, delay, reg; u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); Loading @@ -355,28 +353,28 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, spi_imx->spi_bus_clk = clk; /* set chip select to use */ ctrl |= MX51_ECSPI_CTRL_CS(config->cs); ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); if (config->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); if (spi->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); else cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); if (config->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); if (spi->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); } else { cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); } if (config->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); if (spi->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); else cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); if (spi_imx->usedma) ctrl |= MX51_ECSPI_CTRL_SMC; Loading @@ -385,7 +383,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); if (config->mode & SPI_LOOP) if (spi->mode & SPI_LOOP) reg |= MX51_ECSPI_TESTREG_LBC; else reg &= ~MX51_ECSPI_TESTREG_LBC; Loading Loading @@ -424,12 +422,12 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, return 0; } static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; } static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) { /* drain receive buffer */ while (mx51_ecspi_rx_available(spi_imx)) Loading Loading @@ -459,7 +457,7 @@ static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) * the i.MX35 has a slightly different register layout for bits * we do not use here. */ static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; Loading @@ -471,7 +469,7 @@ static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable writel(val, spi_imx->base + MXC_CSPIINT); } static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) static void mx31_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; Loading @@ -480,11 +478,10 @@ static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) static int mx31_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; int cs = spi_imx->chipselect[config->cs]; reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << MX31_CSPICTRL_DR_SHIFT; Loading @@ -496,14 +493,14 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; } if (config->mode & SPI_CPHA) if (spi->mode & SPI_CPHA) reg |= MX31_CSPICTRL_PHA; if (config->mode & SPI_CPOL) if (spi->mode & SPI_CPOL) reg |= MX31_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) if (spi->mode & SPI_CS_HIGH) reg |= MX31_CSPICTRL_SSPOL; if (cs < 0) reg |= (cs + 32) << if (spi->cs_gpio < 0) reg |= (spi->cs_gpio + 32) << (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : MX31_CSPICTRL_CS_SHIFT); Loading @@ -512,12 +509,12 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, return 0; } static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) static int mx31_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; } static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) static void mx31_reset(struct spi_imx_data *spi_imx) { /* drain receive buffer */ while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) Loading @@ -537,7 +534,7 @@ static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) #define MX21_CSPICTRL_DR_SHIFT 14 #define MX21_CSPICTRL_CS_SHIFT 19 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; Loading @@ -549,7 +546,7 @@ static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable writel(val, spi_imx->base + MXC_CSPIINT); } static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) static void mx21_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; Loading @@ -558,37 +555,36 @@ static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) static int mx21_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; int cs = spi_imx->chipselect[config->cs]; unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << MX21_CSPICTRL_DR_SHIFT; reg |= config->bpw - 1; if (config->mode & SPI_CPHA) if (spi->mode & SPI_CPHA) reg |= MX21_CSPICTRL_PHA; if (config->mode & SPI_CPOL) if (spi->mode & SPI_CPOL) reg |= MX21_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) if (spi->mode & SPI_CS_HIGH) reg |= MX21_CSPICTRL_SSPOL; if (cs < 0) reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; if (spi->cs_gpio < 0) reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT; writel(reg, spi_imx->base + MXC_CSPICTRL); return 0; } static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) static int mx21_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; } static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) static void mx21_reset(struct spi_imx_data *spi_imx) { writel(1, spi_imx->base + MXC_RESET); } Loading @@ -604,7 +600,7 @@ static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) #define MX1_CSPICTRL_MASTER (1 << 10) #define MX1_CSPICTRL_DR_SHIFT 13 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; Loading @@ -616,7 +612,7 @@ static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) writel(val, spi_imx->base + MXC_CSPIINT); } static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) static void mx1_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; Loading @@ -625,18 +621,18 @@ static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) static int mx1_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << MX1_CSPICTRL_DR_SHIFT; reg |= config->bpw - 1; if (config->mode & SPI_CPHA) if (spi->mode & SPI_CPHA) reg |= MX1_CSPICTRL_PHA; if (config->mode & SPI_CPOL) if (spi->mode & SPI_CPOL) reg |= MX1_CSPICTRL_POL; writel(reg, spi_imx->base + MXC_CSPICTRL); Loading @@ -644,12 +640,12 @@ static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, return 0; } static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) static int mx1_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; } static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) static void mx1_reset(struct spi_imx_data *spi_imx) { writel(1, spi_imx->base + MXC_RESET); } Loading Loading @@ -747,15 +743,13 @@ MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); static void spi_imx_chipselect(struct spi_device *spi, int is_active) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); int gpio = spi_imx->chipselect[spi->chip_select]; int active = is_active != BITBANG_CS_INACTIVE; int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); if (!gpio_is_valid(gpio)) if (!gpio_is_valid(spi->cs_gpio)) return; gpio_set_value(gpio, dev_is_lowactive ^ active); gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); } static void spi_imx_push(struct spi_imx_data *spi_imx) Loading Loading @@ -859,8 +853,6 @@ static int spi_imx_setupxfer(struct spi_device *spi, config.bpw = t ? t->bits_per_word : spi->bits_per_word; config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; config.mode = spi->mode; config.cs = spi->chip_select; if (!config.speed_hz) config.speed_hz = spi->max_speed_hz; Loading Loading @@ -891,7 +883,7 @@ static int spi_imx_setupxfer(struct spi_device *spi, return ret; } spi_imx->devtype_data->config(spi_imx, &config); spi_imx->devtype_data->config(spi, &config); return 0; } Loading Loading @@ -1050,6 +1042,8 @@ static int spi_imx_pio_transfer(struct spi_device *spi, struct spi_transfer *transfer) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned long transfer_timeout; unsigned long timeout; spi_imx->tx_buf = transfer->tx_buf; spi_imx->rx_buf = transfer->rx_buf; Loading @@ -1062,7 +1056,15 @@ static int spi_imx_pio_transfer(struct spi_device *spi, spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); wait_for_completion(&spi_imx->xfer_done); transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); timeout = wait_for_completion_timeout(&spi_imx->xfer_done, transfer_timeout); if (!timeout) { dev_err(&spi->dev, "I/O Error in PIO\n"); spi_imx->devtype_data->reset(spi_imx); return -ETIMEDOUT; } return transfer->len; } Loading @@ -1080,14 +1082,12 @@ static int spi_imx_transfer(struct spi_device *spi, static int spi_imx_setup(struct spi_device *spi) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); int gpio = spi_imx->chipselect[spi->chip_select]; dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, spi->mode, spi->bits_per_word, spi->max_speed_hz); if (gpio_is_valid(gpio)) gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); if (gpio_is_valid(spi->cs_gpio)) gpio_direction_output(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); Loading Loading @@ -1137,31 +1137,21 @@ static int spi_imx_probe(struct platform_device *pdev) struct spi_master *master; struct spi_imx_data *spi_imx; struct resource *res; int i, ret, num_cs, irq; int i, ret, irq; if (!np && !mxc_platform_info) { dev_err(&pdev->dev, "can't get the platform data\n"); return -EINVAL; } ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); if (ret < 0) { if (mxc_platform_info) num_cs = mxc_platform_info->num_chipselect; else return ret; } master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data) + sizeof(int) * num_cs); master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); if (!master) return -ENOMEM; platform_set_drvdata(pdev, master); master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); master->bus_num = pdev->id; master->num_chipselect = num_cs; master->bus_num = np ? -1 : pdev->id; spi_imx = spi_master_get_devdata(master); spi_imx->bitbang.master = master; Loading @@ -1170,21 +1160,15 @@ static int spi_imx_probe(struct platform_device *pdev) spi_imx->devtype_data = of_id ? of_id->data : (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; for (i = 0; i < master->num_chipselect; i++) { int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); if (!gpio_is_valid(cs_gpio) && mxc_platform_info) cs_gpio = mxc_platform_info->chipselect[i]; spi_imx->chipselect[i] = cs_gpio; if (!gpio_is_valid(cs_gpio)) continue; if (mxc_platform_info) { master->num_chipselect = mxc_platform_info->num_chipselect; master->cs_gpios = devm_kzalloc(&master->dev, sizeof(int) * master->num_chipselect, GFP_KERNEL); if (!master->cs_gpios) return -ENOMEM; ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], DRIVER_NAME); if (ret) { dev_err(&pdev->dev, "can't get cs gpios\n"); goto out_master_put; } for (i = 0; i < master->num_chipselect; i++) master->cs_gpios[i] = mxc_platform_info->chipselect[i]; } spi_imx->bitbang.chipselect = spi_imx_chipselect; Loading Loading @@ -1267,6 +1251,19 @@ static int spi_imx_probe(struct platform_device *pdev) goto out_clk_put; } for (i = 0; i < master->num_chipselect; i++) { if (!gpio_is_valid(master->cs_gpios[i])) continue; ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i], DRIVER_NAME); if (ret) { dev_err(&pdev->dev, "Can't get CS GPIO %i\n", master->cs_gpios[i]); goto out_clk_put; } } dev_info(&pdev->dev, "probed\n"); clk_disable(spi_imx->clk_ipg); Loading drivers/spi/spi-loopback-test.c +1 −1 Original line number Diff line number Diff line Loading @@ -536,7 +536,7 @@ static int spi_test_check_loopback_result(struct spi_device *spi, mismatch_error: dev_err(&spi->dev, "loopback strangeness - transfer missmatch on byte %04zx - expected 0x%02x, but got 0x%02x\n", "loopback strangeness - transfer mismatch on byte %04zx - expected 0x%02x, but got 0x%02x\n", i, txb, rxb); return -EINVAL; Loading drivers/spi/spi-mpc52xx-psc.c +3 −14 Original line number Diff line number Diff line Loading @@ -42,7 +42,6 @@ struct mpc52xx_psc_spi { u8 bits_per_word; u8 busy; struct workqueue_struct *workqueue; struct work_struct work; struct list_head queue; Loading Loading @@ -299,7 +298,7 @@ static int mpc52xx_psc_spi_transfer(struct spi_device *spi, spin_lock_irqsave(&mps->lock, flags); list_add_tail(&m->queue, &mps->queue); queue_work(mps->workqueue, &mps->work); schedule_work(&mps->work); spin_unlock_irqrestore(&mps->lock, flags); return 0; Loading Loading @@ -425,21 +424,12 @@ static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, INIT_WORK(&mps->work, mpc52xx_psc_spi_work); INIT_LIST_HEAD(&mps->queue); mps->workqueue = create_singlethread_workqueue( dev_name(master->dev.parent)); if (mps->workqueue == NULL) { ret = -EBUSY; goto free_irq; } ret = spi_register_master(master); if (ret < 0) goto unreg_master; goto free_irq; return ret; unreg_master: destroy_workqueue(mps->workqueue); free_irq: free_irq(mps->irq, mps); free_master: Loading Loading @@ -484,8 +474,7 @@ static int mpc52xx_psc_spi_of_remove(struct platform_device *op) struct spi_master *master = spi_master_get(platform_get_drvdata(op)); struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); flush_workqueue(mps->workqueue); destroy_workqueue(mps->workqueue); flush_work(&mps->work); spi_unregister_master(master); free_irq(mps->irq, mps); if (mps->psc) Loading Loading
Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +3 −2 Original line number Diff line number Diff line Loading @@ -11,7 +11,6 @@ Required properties: - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt - fsl,spi-num-chipselects : Contains the number of the chipselect - cs-gpios : Specifies the gpio pins to be used for chipselects. - clocks : Clock specifiers for both ipg and per clocks. - clock-names : Clock names should include both "ipg" and "per" Loading @@ -21,6 +20,9 @@ See the clock consumer binding, Documentation/devicetree/bindings/dma/dma.txt - dma-names: DMA request names should include "tx" and "rx" if present. Obsolete properties: - fsl,spi-num-chipselects : Contains the number of the chipselect Example: ecspi@70010000 { Loading @@ -29,7 +31,6 @@ ecspi@70010000 { compatible = "fsl,imx51-ecspi"; reg = <0x70010000 0x4000>; interrupts = <36>; fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */ <&gpio3 25 0>; /* GPIO3_25 */ dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; Loading
MAINTAINERS +1 −0 Original line number Diff line number Diff line Loading @@ -10799,6 +10799,7 @@ L: linux-spi@vger.kernel.org T: git git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git Q: http://patchwork.kernel.org/project/spi-devel-general/list/ S: Maintained F: Documentation/devicetree/bindings/spi/ F: Documentation/spi/ F: drivers/spi/ F: include/linux/spi/ Loading
drivers/spi/spi-imx.c +94 −97 Original line number Diff line number Diff line Loading @@ -59,8 +59,6 @@ struct spi_imx_config { unsigned int speed_hz; unsigned int bpw; unsigned int mode; u8 cs; }; enum spi_imx_devtype { Loading @@ -76,7 +74,7 @@ struct spi_imx_data; struct spi_imx_devtype_data { void (*intctrl)(struct spi_imx_data *, int); int (*config)(struct spi_imx_data *, struct spi_imx_config *); int (*config)(struct spi_device *, struct spi_imx_config *); void (*trigger)(struct spi_imx_data *); int (*rx_available)(struct spi_imx_data *); void (*reset)(struct spi_imx_data *); Loading Loading @@ -112,7 +110,6 @@ struct spi_imx_data { struct completion dma_tx_completion; const struct spi_imx_devtype_data *devtype_data; int chipselect[0]; }; static inline int is_imx27_cspi(struct spi_imx_data *d) Loading Loading @@ -312,7 +309,7 @@ static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx, (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET); } static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned val = 0; Loading @@ -325,7 +322,7 @@ static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int writel(val, spi_imx->base + MX51_ECSPI_INT); } static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx) { u32 reg; Loading @@ -334,9 +331,10 @@ static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MX51_ECSPI_CTRL); } static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, static int mx51_ecspi_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); u32 ctrl = MX51_ECSPI_CTRL_ENABLE; u32 clk = config->speed_hz, delay, reg; u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); Loading @@ -355,28 +353,28 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, spi_imx->spi_bus_clk = clk; /* set chip select to use */ ctrl |= MX51_ECSPI_CTRL_CS(config->cs); ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET; cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs); cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); if (config->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs); if (spi->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); else cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); if (config->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs); if (spi->mode & SPI_CPOL) { cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); } else { cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); } if (config->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs); if (spi->mode & SPI_CS_HIGH) cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); else cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(config->cs); cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); if (spi_imx->usedma) ctrl |= MX51_ECSPI_CTRL_SMC; Loading @@ -385,7 +383,7 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); reg = readl(spi_imx->base + MX51_ECSPI_TESTREG); if (config->mode & SPI_LOOP) if (spi->mode & SPI_LOOP) reg |= MX51_ECSPI_TESTREG_LBC; else reg &= ~MX51_ECSPI_TESTREG_LBC; Loading Loading @@ -424,12 +422,12 @@ static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx, return 0; } static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR; } static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) static void mx51_ecspi_reset(struct spi_imx_data *spi_imx) { /* drain receive buffer */ while (mx51_ecspi_rx_available(spi_imx)) Loading Loading @@ -459,7 +457,7 @@ static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx) * the i.MX35 has a slightly different register layout for bits * we do not use here. */ static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; Loading @@ -471,7 +469,7 @@ static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable writel(val, spi_imx->base + MXC_CSPIINT); } static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) static void mx31_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; Loading @@ -480,11 +478,10 @@ static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) static int mx31_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER; int cs = spi_imx->chipselect[config->cs]; reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << MX31_CSPICTRL_DR_SHIFT; Loading @@ -496,14 +493,14 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT; } if (config->mode & SPI_CPHA) if (spi->mode & SPI_CPHA) reg |= MX31_CSPICTRL_PHA; if (config->mode & SPI_CPOL) if (spi->mode & SPI_CPOL) reg |= MX31_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) if (spi->mode & SPI_CS_HIGH) reg |= MX31_CSPICTRL_SSPOL; if (cs < 0) reg |= (cs + 32) << if (spi->cs_gpio < 0) reg |= (spi->cs_gpio + 32) << (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT : MX31_CSPICTRL_CS_SHIFT); Loading @@ -512,12 +509,12 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx, return 0; } static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx) static int mx31_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR; } static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) static void mx31_reset(struct spi_imx_data *spi_imx) { /* drain receive buffer */ while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR) Loading @@ -537,7 +534,7 @@ static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx) #define MX21_CSPICTRL_DR_SHIFT 14 #define MX21_CSPICTRL_CS_SHIFT 19 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; Loading @@ -549,7 +546,7 @@ static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable writel(val, spi_imx->base + MXC_CSPIINT); } static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) static void mx21_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; Loading @@ -558,37 +555,36 @@ static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) static int mx21_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER; int cs = spi_imx->chipselect[config->cs]; unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18; reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) << MX21_CSPICTRL_DR_SHIFT; reg |= config->bpw - 1; if (config->mode & SPI_CPHA) if (spi->mode & SPI_CPHA) reg |= MX21_CSPICTRL_PHA; if (config->mode & SPI_CPOL) if (spi->mode & SPI_CPOL) reg |= MX21_CSPICTRL_POL; if (config->mode & SPI_CS_HIGH) if (spi->mode & SPI_CS_HIGH) reg |= MX21_CSPICTRL_SSPOL; if (cs < 0) reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT; if (spi->cs_gpio < 0) reg |= (spi->cs_gpio + 32) << MX21_CSPICTRL_CS_SHIFT; writel(reg, spi_imx->base + MXC_CSPICTRL); return 0; } static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx) static int mx21_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR; } static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) static void mx21_reset(struct spi_imx_data *spi_imx) { writel(1, spi_imx->base + MXC_RESET); } Loading @@ -604,7 +600,7 @@ static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx) #define MX1_CSPICTRL_MASTER (1 << 10) #define MX1_CSPICTRL_DR_SHIFT 13 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable) { unsigned int val = 0; Loading @@ -616,7 +612,7 @@ static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable) writel(val, spi_imx->base + MXC_CSPIINT); } static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) static void mx1_trigger(struct spi_imx_data *spi_imx) { unsigned int reg; Loading @@ -625,18 +621,18 @@ static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx) writel(reg, spi_imx->base + MXC_CSPICTRL); } static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, struct spi_imx_config *config) static int mx1_config(struct spi_device *spi, struct spi_imx_config *config) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER; reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) << MX1_CSPICTRL_DR_SHIFT; reg |= config->bpw - 1; if (config->mode & SPI_CPHA) if (spi->mode & SPI_CPHA) reg |= MX1_CSPICTRL_PHA; if (config->mode & SPI_CPOL) if (spi->mode & SPI_CPOL) reg |= MX1_CSPICTRL_POL; writel(reg, spi_imx->base + MXC_CSPICTRL); Loading @@ -644,12 +640,12 @@ static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx, return 0; } static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx) static int mx1_rx_available(struct spi_imx_data *spi_imx) { return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR; } static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx) static void mx1_reset(struct spi_imx_data *spi_imx) { writel(1, spi_imx->base + MXC_RESET); } Loading Loading @@ -747,15 +743,13 @@ MODULE_DEVICE_TABLE(of, spi_imx_dt_ids); static void spi_imx_chipselect(struct spi_device *spi, int is_active) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); int gpio = spi_imx->chipselect[spi->chip_select]; int active = is_active != BITBANG_CS_INACTIVE; int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH); if (!gpio_is_valid(gpio)) if (!gpio_is_valid(spi->cs_gpio)) return; gpio_set_value(gpio, dev_is_lowactive ^ active); gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active); } static void spi_imx_push(struct spi_imx_data *spi_imx) Loading Loading @@ -859,8 +853,6 @@ static int spi_imx_setupxfer(struct spi_device *spi, config.bpw = t ? t->bits_per_word : spi->bits_per_word; config.speed_hz = t ? t->speed_hz : spi->max_speed_hz; config.mode = spi->mode; config.cs = spi->chip_select; if (!config.speed_hz) config.speed_hz = spi->max_speed_hz; Loading Loading @@ -891,7 +883,7 @@ static int spi_imx_setupxfer(struct spi_device *spi, return ret; } spi_imx->devtype_data->config(spi_imx, &config); spi_imx->devtype_data->config(spi, &config); return 0; } Loading Loading @@ -1050,6 +1042,8 @@ static int spi_imx_pio_transfer(struct spi_device *spi, struct spi_transfer *transfer) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); unsigned long transfer_timeout; unsigned long timeout; spi_imx->tx_buf = transfer->tx_buf; spi_imx->rx_buf = transfer->rx_buf; Loading @@ -1062,7 +1056,15 @@ static int spi_imx_pio_transfer(struct spi_device *spi, spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE); wait_for_completion(&spi_imx->xfer_done); transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len); timeout = wait_for_completion_timeout(&spi_imx->xfer_done, transfer_timeout); if (!timeout) { dev_err(&spi->dev, "I/O Error in PIO\n"); spi_imx->devtype_data->reset(spi_imx); return -ETIMEDOUT; } return transfer->len; } Loading @@ -1080,14 +1082,12 @@ static int spi_imx_transfer(struct spi_device *spi, static int spi_imx_setup(struct spi_device *spi) { struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master); int gpio = spi_imx->chipselect[spi->chip_select]; dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__, spi->mode, spi->bits_per_word, spi->max_speed_hz); if (gpio_is_valid(gpio)) gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); if (gpio_is_valid(spi->cs_gpio)) gpio_direction_output(spi->cs_gpio, spi->mode & SPI_CS_HIGH ? 0 : 1); spi_imx_chipselect(spi, BITBANG_CS_INACTIVE); Loading Loading @@ -1137,31 +1137,21 @@ static int spi_imx_probe(struct platform_device *pdev) struct spi_master *master; struct spi_imx_data *spi_imx; struct resource *res; int i, ret, num_cs, irq; int i, ret, irq; if (!np && !mxc_platform_info) { dev_err(&pdev->dev, "can't get the platform data\n"); return -EINVAL; } ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs); if (ret < 0) { if (mxc_platform_info) num_cs = mxc_platform_info->num_chipselect; else return ret; } master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data) + sizeof(int) * num_cs); master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data)); if (!master) return -ENOMEM; platform_set_drvdata(pdev, master); master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32); master->bus_num = pdev->id; master->num_chipselect = num_cs; master->bus_num = np ? -1 : pdev->id; spi_imx = spi_master_get_devdata(master); spi_imx->bitbang.master = master; Loading @@ -1170,21 +1160,15 @@ static int spi_imx_probe(struct platform_device *pdev) spi_imx->devtype_data = of_id ? of_id->data : (struct spi_imx_devtype_data *)pdev->id_entry->driver_data; for (i = 0; i < master->num_chipselect; i++) { int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); if (!gpio_is_valid(cs_gpio) && mxc_platform_info) cs_gpio = mxc_platform_info->chipselect[i]; spi_imx->chipselect[i] = cs_gpio; if (!gpio_is_valid(cs_gpio)) continue; if (mxc_platform_info) { master->num_chipselect = mxc_platform_info->num_chipselect; master->cs_gpios = devm_kzalloc(&master->dev, sizeof(int) * master->num_chipselect, GFP_KERNEL); if (!master->cs_gpios) return -ENOMEM; ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i], DRIVER_NAME); if (ret) { dev_err(&pdev->dev, "can't get cs gpios\n"); goto out_master_put; } for (i = 0; i < master->num_chipselect; i++) master->cs_gpios[i] = mxc_platform_info->chipselect[i]; } spi_imx->bitbang.chipselect = spi_imx_chipselect; Loading Loading @@ -1267,6 +1251,19 @@ static int spi_imx_probe(struct platform_device *pdev) goto out_clk_put; } for (i = 0; i < master->num_chipselect; i++) { if (!gpio_is_valid(master->cs_gpios[i])) continue; ret = devm_gpio_request(&pdev->dev, master->cs_gpios[i], DRIVER_NAME); if (ret) { dev_err(&pdev->dev, "Can't get CS GPIO %i\n", master->cs_gpios[i]); goto out_clk_put; } } dev_info(&pdev->dev, "probed\n"); clk_disable(spi_imx->clk_ipg); Loading
drivers/spi/spi-loopback-test.c +1 −1 Original line number Diff line number Diff line Loading @@ -536,7 +536,7 @@ static int spi_test_check_loopback_result(struct spi_device *spi, mismatch_error: dev_err(&spi->dev, "loopback strangeness - transfer missmatch on byte %04zx - expected 0x%02x, but got 0x%02x\n", "loopback strangeness - transfer mismatch on byte %04zx - expected 0x%02x, but got 0x%02x\n", i, txb, rxb); return -EINVAL; Loading
drivers/spi/spi-mpc52xx-psc.c +3 −14 Original line number Diff line number Diff line Loading @@ -42,7 +42,6 @@ struct mpc52xx_psc_spi { u8 bits_per_word; u8 busy; struct workqueue_struct *workqueue; struct work_struct work; struct list_head queue; Loading Loading @@ -299,7 +298,7 @@ static int mpc52xx_psc_spi_transfer(struct spi_device *spi, spin_lock_irqsave(&mps->lock, flags); list_add_tail(&m->queue, &mps->queue); queue_work(mps->workqueue, &mps->work); schedule_work(&mps->work); spin_unlock_irqrestore(&mps->lock, flags); return 0; Loading Loading @@ -425,21 +424,12 @@ static int mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr, INIT_WORK(&mps->work, mpc52xx_psc_spi_work); INIT_LIST_HEAD(&mps->queue); mps->workqueue = create_singlethread_workqueue( dev_name(master->dev.parent)); if (mps->workqueue == NULL) { ret = -EBUSY; goto free_irq; } ret = spi_register_master(master); if (ret < 0) goto unreg_master; goto free_irq; return ret; unreg_master: destroy_workqueue(mps->workqueue); free_irq: free_irq(mps->irq, mps); free_master: Loading Loading @@ -484,8 +474,7 @@ static int mpc52xx_psc_spi_of_remove(struct platform_device *op) struct spi_master *master = spi_master_get(platform_get_drvdata(op)); struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master); flush_workqueue(mps->workqueue); destroy_workqueue(mps->workqueue); flush_work(&mps->work); spi_unregister_master(master); free_irq(mps->irq, mps); if (mps->psc) Loading