Merge remote-tracking branches 'spi/topic/bfin-sport', 'spi/topic/bfin5xx',...

- #size-cells     - should be zero.

- compatible      - name of SPI bus controller following generic names

		recommended practice.

- cs-gpios	  - (optional) gpios chip select.

No other properties are required in the SPI bus node.  It is assumed

that a driver for an SPI bus device will understand that it is an SPI bus.

However, the binding does not attempt to define the specific method for

chip selects.  Individual drivers can define additional properties to

support describing the chip select layout.

Optional property:

- num-cs : total number of chipselects

Optional properties:

- cs-gpios	  - gpios chip select.

- num-cs	  - total number of chipselects.

If cs-gpios is used the number of chip select will automatically increased

with max(cs-gpios > hw cs)

If cs-gpios is used the number of chip selects will be increased automatically

with max(cs-gpios > hw cs).

So if for example the controller has 2 CS lines, and the cs-gpios

property looks like this:

contain the following properties.

- reg             - (required) chip select address of device.

- compatible      - (required) name of SPI device following generic names

    		recommended practice

- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz

		recommended practice.

- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz.

- spi-cpol        - (optional) Empty property indicating device requires

    		inverse clock polarity (CPOL) mode

		inverse clock polarity (CPOL) mode.

- spi-cpha        - (optional) Empty property indicating device requires

    		shifted clock phase (CPHA) mode

		shifted clock phase (CPHA) mode.

- spi-cs-high     - (optional) Empty property indicating device requires

    		chip select active high

		chip select active high.

- spi-3wire       - (optional) Empty property indicating device requires

		3-wire mode.

- spi-lsb-first   - (optional) Empty property indicating device requires

		LSB first mode.

- spi-tx-bus-width - (optional) The bus width(number of data wires) that

- spi-tx-bus-width - (optional) The bus width (number of data wires) that is

                      used for MOSI. Defaults to 1 if not present.

- spi-rx-bus-width - (optional) The bus width(number of data wires) that

- spi-rx-bus-width - (optional) The bus width (number of data wires) that is

                      used for MISO. Defaults to 1 if not present.

- spi-rx-delay-us  - (optional) Microsecond delay after a read transfer.

- spi-tx-delay-us  - (optional) Microsecond delay after a write transfer.

Some SPI controllers and devices support Dual and Quad SPI transfer mode.

It allows data in the SPI system to be transferred in 2 wires(DUAL) or 4 wires(QUAD).

It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4

wires (QUAD).

Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is

only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).

Dual/Quad mode is not allowed when 3-wire mode is used.

Serial Peripheral Interface on Cirrus Logic CL-PS71xx, EP72xx, EP73xx

Required properties

- #address-cells: must be <1>

- #size-cells: must be <0>

- compatible: should include "cirrus,ep7209-spi"

- reg: Address and length of one register range

- interrupts: one interrupt line

- clocks: One entry, refers to the SPI bus clock

- cs-gpios: Specifies the gpio pins to be used for chipselects.

	    See: Documentation/devicetree/bindings/spi/spi-bus.txt

An additional register is present in the system controller,

which is assumed to be in the same device tree, with and marked

as compatible with "cirrus,ep7209-syscon3".

Example:

spi@80000500 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "cirrus,ep7209-spi";

	reg = <0x80000500 0x4>;

	interrupts = <15>;

	clocks = <&clks CLPS711X_CLK_SPI>;

	status = "disabled";

};

syscon3: syscon@80002200 {

	compatible = "cirrus,ep7209-syscon3", "syscon";

	reg = <0x80002200 0x40>;

};

	IP to the interrupt controller within the SoC. Possible values

	are 0 and 1. Manual says one of the two possible interrupt

	lines can be tied to the interrupt controller. Set this

	based on a specifc SoC configuration.

	based on a specific SoC configuration.

- interrupts: interrupt number mapped to CPU.

- clocks: spi clk phandle

		      chipselect register and offset of that register.

NOTE: TI QSPI controller requires different pinmux and IODelay

paramaters for Mode-0 and Mode-3 operations, which needs to be set up by

parameters for Mode-0 and Mode-3 operations, which needs to be set up by

the bootloader (U-Boot). Default configuration only supports Mode-0

operation. Hence, "spi-cpol" and "spi-cpha" DT properties cannot be

specified in the slave nodes of TI QSPI controller without appropriate

	/* Pin request list */

	u16 *pin_req;

	/* Driver message queue */

	struct workqueue_struct *workqueue;

	struct work_struct pump_messages;

	spinlock_t lock;

	struct list_head queue;

	drv_data->cur_msg = NULL;

	drv_data->cur_transfer = NULL;

	drv_data->cur_chip = NULL;

	queue_work(drv_data->workqueue, &drv_data->pump_messages);

	schedule_work(&drv_data->pump_messages);

	spin_unlock_irqrestore(&drv_data->lock, flags);

	if (!drv_data->cs_change)

	list_add_tail(&msg->queue, &drv_data->queue);

	if (drv_data->run && !drv_data->busy)

		queue_work(drv_data->workqueue, &drv_data->pump_messages);

		schedule_work(&drv_data->pump_messages);

	spin_unlock_irqrestore(&drv_data->lock, flags);

	tasklet_init(&drv_data->pump_transfers,

		     bfin_sport_spi_pump_transfers, (unsigned long)drv_data);

	/* init messages workqueue */

	INIT_WORK(&drv_data->pump_messages, bfin_sport_spi_pump_messages);

	drv_data->workqueue =

	    create_singlethread_workqueue(dev_name(drv_data->master->dev.parent));

	if (drv_data->workqueue == NULL)

		return -EBUSY;

	return 0;

}

	drv_data->cur_chip = NULL;

	spin_unlock_irqrestore(&drv_data->lock, flags);

	queue_work(drv_data->workqueue, &drv_data->pump_messages);

	schedule_work(&drv_data->pump_messages);

	return 0;

}

	if (status)

		return status;

	destroy_workqueue(drv_data->workqueue);

	flush_work(&drv_data->pump_messages);

	return 0;

}