power: reset: at91-poweroff: switch to slow clock before shutdown

The SAMA5D2 NRST input signal is resynchronized with the SLCK clock and it
can take up to 2 SLCK cycles (about 90us) for the internal reset to be
effective. During this delay, the VDDCORE current consumption may still be
high (application-dependent) with the VDDCORE regulator already OFF. Under
such conditions, VDDCORE may operate below its operating range leading to
potential register corruption.

To prevent such situation, it is recommended to decrease significantly the
power consumption of the device once the voltage regulator is  turned-off.
This can be achieved by operating the device at a much lower low frequency.

To solve this switch the master clock to slock clock just before writing
shutdown command to shutdown controller.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Suggested-by: Patrice Vilchez <patrice.vilchez@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>