msm: timer: SMP timer support for msm
The msm provides timer hardware that is private to each core. Each timer has separate counter and match registers, so we create separate clock_event_devices for each core. For the global clocksource, use cpu 0's counter. Signed-off-by:Jeff Ohlstein <johlstei@codeaurora.org> Signed-off-by:
David Brown <davidb@codeaurora.org>
parent
7b181446
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