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Commit 7bed9246 authored by Elaine Zhang's avatar Elaine Zhang Committed by Heiko Stuebner
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clk: rockchip: add new pll-type for rk3328



The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask, the rk3328 soc
pll mode only one bit(rk3036 soc have two bits)
so these should be independent and separate from
the series of rk3328s.

Signed-off-by: default avatarElaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 4d3e84f9
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