Commit ff730e96 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Split helper_msr_i_pstate into 3 



The EL0+UMA check is unique to DAIF.  While SPSel had avoided the
check by nature of already checking EL >= 1, the other post v8.0
extensions to MSR (imm) allow EL0 and do not require UMA.  Avoid
the unconditional write to pc and use raise_exception_ra to unwind.

Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-5-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent cb570bd3

target/arm/helper-a64.c

+30 −0
Original line number Diff line number Diff line
@@ -61,6 +61,36 @@ uint64_t HELPER(rbit64)(uint64_t x) 
    return revbit64(x);

}



void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)

{

    update_spsel(env, imm);

}



static void daif_check(CPUARMState *env, uint32_t op,

                       uint32_t imm, uintptr_t ra)

{

    /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set.  */

    if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {

        raise_exception_ra(env, EXCP_UDEF,

                           syn_aa64_sysregtrap(0, extract32(op, 0, 3),

                                               extract32(op, 3, 3), 4,

                                               imm, 0x1f, 0),

                           exception_target_el(env), ra);

    }

}



void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm)

{

    daif_check(env, 0x1e, imm, GETPC());

    env->daif |= (imm << 6) & PSTATE_DAIF;

}



void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm)

{

    daif_check(env, 0x1f, imm, GETPC());

    env->daif &= ~((imm << 6) & PSTATE_DAIF);

}



/* Convert a softfloat float_relation_ (as returned by

 * the float*_compare functions) to the correct ARM

 * NZCV flag state.

target/arm/helper-a64.h

+3 −0
Original line number Diff line number Diff line
@@ -19,6 +19,9 @@ 
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)

DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)

DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)

DEF_HELPER_2(msr_i_spsel, void, env, i32)

DEF_HELPER_2(msr_i_daifset, void, env, i32)

DEF_HELPER_2(msr_i_daifclear, void, env, i32)

DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)

DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)

DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)

target/arm/helper.h

+0 −1
Original line number Diff line number Diff line
@@ -77,7 +77,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) 
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)

DEF_HELPER_2(get_cp_reg64, i64, env, ptr)



DEF_HELPER_3(msr_i_pstate, void, env, i32, i32)

DEF_HELPER_1(clear_pstate_ss, void, env)



DEF_HELPER_2(get_r13_banked, i32, env, i32)

target/arm/internals.h

+15 −0
Original line number Diff line number Diff line
@@ -968,4 +968,19 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, 
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,

                                   ARMMMUIdx mmu_idx, bool data);



static inline int exception_target_el(CPUARMState *env)

{

    int target_el = MAX(1, arm_current_el(env));



    /*

     * No such thing as secure EL1 if EL3 is aarch32,

     * so update the target EL to EL3 in this case.

     */

    if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {

        target_el = 3;

    }



    return target_el;

}



#endif

target/arm/op_helper.c

+0 −42
Original line number Diff line number Diff line
@@ -68,20 +68,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, 
    cpu_loop_exit_restore(cs, ra);

}



static int exception_target_el(CPUARMState *env)

{

    int target_el = MAX(1, arm_current_el(env));



    /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL

     * to EL3 in this case.

     */

    if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {

        target_el = 3;

    }



    return target_el;

}



uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,

                          uint32_t maxindex)

{
@@ -875,34 +861,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) 
    return res;

}



void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)

{

    /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.

     * Note that SPSel is never OK from EL0; we rely on handle_msr_i()

     * to catch that case at translate time.

     */

    if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {

        uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3),

                                                extract32(op, 3, 3), 4,

                                                imm, 0x1f, 0);

        raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));

    }



    switch (op) {

    case 0x05: /* SPSel */

        update_spsel(env, imm);

        break;

    case 0x1e: /* DAIFSet */

        env->daif |= (imm << 6) & PSTATE_DAIF;

        break;

    case 0x1f: /* DAIFClear */

        env->daif &= ~((imm << 6) & PSTATE_DAIF);

        break;

    default:

        g_assert_not_reached();

    }

}



void HELPER(clear_pstate_ss)(CPUARMState *env)

{

    env->pstate &= ~PSTATE_SS;