Commit cb570bd3 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement ARMv8.0-PredInv 



Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-4-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 9888bd1e

target/arm/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -2022,6 +2022,7 @@ static void arm_max_initfn(Object *obj) 
            t = FIELD_DP32(t, ID_ISAR6, DP, 1);

            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);

            t = FIELD_DP32(t, ID_ISAR6, SB, 1);

            t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);

            cpu->isar.id_isar6 = t;



            t = cpu->id_mmfr4;

target/arm/cpu.h

+12 −1
Original line number Diff line number Diff line
@@ -1060,7 +1060,8 @@ void pmu_init(ARMCPU *cpu); 
#define SCTLR_R       (1U << 9) /* up to v6; RAZ in v7 */

#define SCTLR_UMA     (1U << 9) /* v8 onward, AArch64 only */

#define SCTLR_F       (1U << 10) /* up to v6 */

#define SCTLR_SW      (1U << 10) /* v7, RES0 in v8 */

#define SCTLR_SW      (1U << 10) /* v7 */

#define SCTLR_EnRCTX  (1U << 10) /* in v8.0-PredInv */

#define SCTLR_Z       (1U << 11) /* in v7, RES1 in v8 */

#define SCTLR_EOS     (1U << 11) /* v8.5-ExS */

#define SCTLR_I       (1U << 12)
@@ -3312,6 +3313,11 @@ static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) 
    return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;

}



static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)

{

    return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;

}



static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)

{

    /*
@@ -3455,6 +3461,11 @@ static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) 
    return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;

}



static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;

}



static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)

{

    /* We always set the AdvSIMD and FP fields identically wrt FP16.  */

target/arm/cpu64.c

+2 −0
Original line number Diff line number Diff line
@@ -319,6 +319,7 @@ static void aarch64_max_initfn(Object *obj) 
        t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);

        t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);

        t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);

        t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);

        cpu->isar.id_aa64isar1 = t;



        t = cpu->isar.id_aa64pfr0;
@@ -351,6 +352,7 @@ static void aarch64_max_initfn(Object *obj) 
        u = FIELD_DP32(u, ID_ISAR6, DP, 1);

        u = FIELD_DP32(u, ID_ISAR6, FHM, 1);

        u = FIELD_DP32(u, ID_ISAR6, SB, 1);

        u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);

        cpu->isar.id_isar6 = u;



        /*

target/arm/helper.c

+55 −0
Original line number Diff line number Diff line
@@ -5719,6 +5719,50 @@ static const ARMCPRegInfo pauth_reginfo[] = { 
};

#endif



static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,

                                     bool isread)

{

    int el = arm_current_el(env);



    if (el == 0) {

        uint64_t sctlr = arm_sctlr(env, el);

        if (!(sctlr & SCTLR_EnRCTX)) {

            return CP_ACCESS_TRAP;

        }

    } else if (el == 1) {

        uint64_t hcr = arm_hcr_el2_eff(env);

        if (hcr & HCR_NV) {

            return CP_ACCESS_TRAP_EL2;

        }

    }

    return CP_ACCESS_OK;

}



static const ARMCPRegInfo predinv_reginfo[] = {

    { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,

      .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },

    { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,

      .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },

    { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,

      .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },

    /*

     * Note the AArch32 opcodes have a different OPC1.

     */

    { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,

      .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },

    { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,

      .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },

    { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,

      .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,

      .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },

    REGINFO_SENTINEL

};



void register_cp_regs_for_features(ARMCPU *cpu)

{

    /* Register all the coprocessor registers based on feature bits */
@@ -6618,6 +6662,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
        define_arm_cp_regs(cpu, pauth_reginfo);

    }

#endif



    /*

     * While all v8.0 cpus support aarch64, QEMU does have configurations

     * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,

     * which will set ID_ISAR6.

     */

    if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)

        ? cpu_isar_feature(aa64_predinv, cpu)

        : cpu_isar_feature(aa32_predinv, cpu)) {

        define_arm_cp_regs(cpu, predinv_reginfo);

    }

}



void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)