Commit 9888bd1e authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement ARMv8.0-SB 



Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20190301200501.16533-3-richard.henderson@linaro.org
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 64e40755

linux-user/elfload.c

+1 −0
Original line number Diff line number Diff line
@@ -604,6 +604,7 @@ static uint32_t get_elf_hwcap(void) 
    GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);

    GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);

    GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);

    GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);



#undef GET_FEATURE_ID

target/arm/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -2021,6 +2021,7 @@ static void arm_max_initfn(Object *obj) 
            t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);

            t = FIELD_DP32(t, ID_ISAR6, DP, 1);

            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);

            t = FIELD_DP32(t, ID_ISAR6, SB, 1);

            cpu->isar.id_isar6 = t;



            t = cpu->id_mmfr4;

target/arm/cpu.h

+10 −0
Original line number Diff line number Diff line
@@ -3307,6 +3307,11 @@ static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) 
    return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;

}



static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)

{

    return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;

}



static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)

{

    /*
@@ -3445,6 +3450,11 @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) 
             FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;

}



static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)

{

    return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;

}



static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)

{

    /* We always set the AdvSIMD and FP fields identically wrt FP16.  */

target/arm/cpu64.c

+2 −0
Original line number Diff line number Diff line
@@ -318,6 +318,7 @@ static void aarch64_max_initfn(Object *obj) 
        t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);

        t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);

        t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);

        t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);

        cpu->isar.id_aa64isar1 = t;



        t = cpu->isar.id_aa64pfr0;
@@ -349,6 +350,7 @@ static void aarch64_max_initfn(Object *obj) 
        u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);

        u = FIELD_DP32(u, ID_ISAR6, DP, 1);

        u = FIELD_DP32(u, ID_ISAR6, FHM, 1);

        u = FIELD_DP32(u, ID_ISAR6, SB, 1);

        cpu->isar.id_isar6 = u;



        /*

target/arm/translate-a64.c

+14 −0
Original line number Diff line number Diff line
@@ -1637,7 +1637,21 @@ static void handle_sync(DisasContext *s, uint32_t insn, 
        reset_btype(s);

        gen_goto_tb(s, 0, s->pc);

        return;



    case 7: /* SB */

        if (crm != 0 || !dc_isar_feature(aa64_sb, s)) {

            goto do_unallocated;

        }

        /*

         * TODO: There is no speculation barrier opcode for TCG;

         * MB and end the TB instead.

         */

        tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);

        gen_goto_tb(s, 0, s->pc);

        return;



    default:

    do_unallocated:

        unallocated_encoding(s);

        return;

    }