Commit ef475b5d authored by Peter Maydell's avatar Peter Maydell
Browse files

Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20170907' into staging 

target-arm:
 * cleanups converting to DEFINE_PROP_LINK
 * allwinner-a10: mark as not user-creatable
 * initial patches working towards ARMv8M support
 * implement generating aborts on memory transaction failures
 * make BXJ behave correctly (ie not UNDEF) on ARMv6-and-later

# gpg: Signature made Thu 07 Sep 2017 14:26:07 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20170907: (31 commits)
  target/arm: Add Jazelle feature
  target/arm: Implement new do_transaction_failed hook
  hw/arm: Set ignore_memory_transaction_failures for most ARM boards
  boards.h: Define new flag ignore_memory_transaction_failures
  target/arm: Implement BXNS, and banked stack pointers
  target/arm: Move regime_is_secure() to target/arm/internals.h
  target/arm: Make CFSR register banked for v8M
  target/arm: Make MMFAR banked for v8M
  target/arm: Make CCR register banked for v8M
  target/arm: Make MPU_CTRL register banked for v8M
  target/arm: Make MPU_RNR register banked for v8M
  target/arm: Make MPU_RBAR, MPU_RLAR banked for v8M
  target/arm: Make MPU_MAIR0, MPU_MAIR1 registers banked for v8M
  target/arm: Make VTOR register banked for v8M
  nvic: Add NS alias SCS region
  target/arm: Make CONTROL register banked for v8M
  target/arm: Make FAULTMASK register banked for v8M
  target/arm: Make PRIMASK register banked for v8M
  target/arm: Make BASEPRI register banked for v8M
  target/arm: Add MMU indexes for secure v8M
  ...

# Conflicts:
#	target/arm/translate.c
parents 7794b34e c99a55d3

hw/arm/allwinner-a10.c

+2 −0
Original line number Diff line number Diff line
@@ -118,6 +118,8 @@ static void aw_a10_class_init(ObjectClass *oc, void *data) 
    DeviceClass *dc = DEVICE_CLASS(oc);



    dc->realize = aw_a10_realize;

    /* Reason: Uses serial_hds in realize and nd_table in instance_init */

    dc->user_creatable = false;

}



static const TypeInfo aw_a10_type_info = {

hw/arm/armv7m.c

+4 −12
Original line number Diff line number Diff line
@@ -97,12 +97,6 @@ static void bitband_init(Object *obj) 
    BitBandState *s = BITBAND(obj);

    SysBusDevice *dev = SYS_BUS_DEVICE(obj);



    object_property_add_link(obj, "source-memory",

                             TYPE_MEMORY_REGION,

                             (Object **)&s->source_memory,

                             qdev_prop_allow_set_link_before_realize,

                             OBJ_PROP_LINK_UNREF_ON_RELEASE,

                             &error_abort);

    memory_region_init_io(&s->iomem, obj, &bitband_ops, s,

                          "bitband", 0x02000000);

    sysbus_init_mmio(dev, &s->iomem);
@@ -138,12 +132,6 @@ static void armv7m_instance_init(Object *obj) 


    /* Can't init the cpu here, we don't yet know which model to use */



    object_property_add_link(obj, "memory",

                             TYPE_MEMORY_REGION,

                             (Object **)&s->board_memory,

                             qdev_prop_allow_set_link_before_realize,

                             OBJ_PROP_LINK_UNREF_ON_RELEASE,

                             &error_abort);

    memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);



    object_initialize(&s->nvic, sizeof(s->nvic), TYPE_NVIC);
@@ -254,6 +242,8 @@ static void armv7m_realize(DeviceState *dev, Error **errp) 


static Property armv7m_properties[] = {

    DEFINE_PROP_STRING("cpu-model", ARMv7MState, cpu_model),

    DEFINE_PROP_LINK("memory", ARMv7MState, board_memory, TYPE_MEMORY_REGION,

                     MemoryRegion *),

    DEFINE_PROP_END_OF_LIST(),

};
@@ -349,6 +339,8 @@ void armv7m_load_kernel(ARMCPU *cpu, const char *kernel_filename, int mem_size) 


static Property bitband_properties[] = {

    DEFINE_PROP_UINT32("base", BitBandState, base, 0),

    DEFINE_PROP_LINK("source-memory", BitBandState, source_memory,

                     TYPE_MEMORY_REGION, MemoryRegion *),

    DEFINE_PROP_END_OF_LIST(),

};

hw/arm/aspeed.c

+3 −0
Original line number Diff line number Diff line
@@ -270,6 +270,7 @@ static void palmetto_bmc_class_init(ObjectClass *oc, void *data) 
    mc->no_floppy = 1;

    mc->no_cdrom = 1;

    mc->no_parallel = 1;

    mc->ignore_memory_transaction_failures = true;

}



static const TypeInfo palmetto_bmc_type = {
@@ -302,6 +303,7 @@ static void ast2500_evb_class_init(ObjectClass *oc, void *data) 
    mc->no_floppy = 1;

    mc->no_cdrom = 1;

    mc->no_parallel = 1;

    mc->ignore_memory_transaction_failures = true;

}



static const TypeInfo ast2500_evb_type = {
@@ -326,6 +328,7 @@ static void romulus_bmc_class_init(ObjectClass *oc, void *data) 
    mc->no_floppy = 1;

    mc->no_cdrom = 1;

    mc->no_parallel = 1;

    mc->ignore_memory_transaction_failures = true;

}



static const TypeInfo romulus_bmc_type = {

hw/arm/collie.c

+1 −0
Original line number Diff line number Diff line
@@ -64,6 +64,7 @@ static void collie_machine_init(MachineClass *mc) 
{

    mc->desc = "Sharp SL-5500 (Collie) PDA (SA-1110)";

    mc->init = collie_init;

    mc->ignore_memory_transaction_failures = true;

}



DEFINE_MACHINE("collie", collie_machine_init)

hw/arm/cubieboard.c

+1 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ static void cubieboard_machine_init(MachineClass *mc) 
    mc->init = cubieboard_init;

    mc->block_default_type = IF_IDE;

    mc->units_per_default_bus = 1;

    mc->ignore_memory_transaction_failures = true;

}



DEFINE_MACHINE("cubieboard", cubieboard_machine_init)