Commit c99a55d3 authored by Portia Stephens's avatar Portia Stephens Committed by Peter Maydell
Browse files

target/arm: Add Jazelle feature 



This adds a feature bit indicating support of the (trivial) Jazelle
implementation if ARM_FEATURE_V6 is set or if the processor is arm926
or arm1026.  This fixes the issue that any BXJ instruction will
result in an illegal_op.  BXJ instructions will now check if the
architecture supports ARM_FEATURE_JAZELLE.

Signed-off-by: default avatarPortia Stephens <portia.stephens@xilinx.com>
Reviewed-by: default avatarAlistair Francis <alistair.francis@xilinx.com>
Message-id: 20170905211232.11092-1-portia.stephens@xilinx.com
[PMM: edited commit message and comment text a bit]
Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent c79c0a31

target/arm/cpu.c

+3 −0
Original line number Diff line number Diff line
@@ -712,6 +712,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) 
    }

    if (arm_feature(env, ARM_FEATURE_V6)) {

        set_feature(env, ARM_FEATURE_V5);

        set_feature(env, ARM_FEATURE_JAZELLE);

        if (!arm_feature(env, ARM_FEATURE_M)) {

            set_feature(env, ARM_FEATURE_AUXCR);

        }
@@ -927,6 +928,7 @@ static void arm926_initfn(Object *obj) 
    set_feature(&cpu->env, ARM_FEATURE_VFP);

    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);

    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);

    set_feature(&cpu->env, ARM_FEATURE_JAZELLE);

    cpu->midr = 0x41069265;

    cpu->reset_fpsid = 0x41011090;

    cpu->ctr = 0x1dd20d2;
@@ -956,6 +958,7 @@ static void arm1026_initfn(Object *obj) 
    set_feature(&cpu->env, ARM_FEATURE_AUXCR);

    set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);

    set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);

    set_feature(&cpu->env, ARM_FEATURE_JAZELLE);

    cpu->midr = 0x4106a262;

    cpu->reset_fpsid = 0x410110a0;

    cpu->ctr = 0x1dd20d2;

target/arm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -1296,6 +1296,7 @@ enum arm_features { 
    ARM_FEATURE_PMU, /* has PMU support */

    ARM_FEATURE_VBAR, /* has cp15 VBAR */

    ARM_FEATURE_M_SECURITY, /* M profile Security Extension */

    ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */

};



static inline int arm_feature(CPUARMState *env, int feature)

target/arm/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
#define ENABLE_ARCH_5     arm_dc_feature(s, ARM_FEATURE_V5)

/* currently all emulated v5 cores are also v5TE, so don't bother */

#define ENABLE_ARCH_5TE   arm_dc_feature(s, ARM_FEATURE_V5)

#define ENABLE_ARCH_5J    0

#define ENABLE_ARCH_5J    arm_dc_feature(s, ARM_FEATURE_JAZELLE)

#define ENABLE_ARCH_6     arm_dc_feature(s, ARM_FEATURE_V6)

#define ENABLE_ARCH_6K    arm_dc_feature(s, ARM_FEATURE_V6K)

#define ENABLE_ARCH_6T2   arm_dc_feature(s, ARM_FEATURE_THUMB2)