Commit ecf5e8ea authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Make MPU_CTRL register banked for v8M 



Make the MPU_CTRL register banked if v8M security extensions are
enabled.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-16-git-send-email-peter.maydell@linaro.org
parent 1bc04a88

hw/intc/armv7m_nvic.c

+5 −4
Original line number Diff line number Diff line
@@ -541,7 +541,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 
        return cpu->pmsav7_dregion << 8;

        break;

    case 0xd94: /* MPU_CTRL */

        return cpu->env.v7m.mpu_ctrl;

        return cpu->env.v7m.mpu_ctrl[attrs.secure];

    case 0xd98: /* MPU_RNR */

        return cpu->env.pmsav7.rnr[attrs.secure];

    case 0xd9c: /* MPU_RBAR */
@@ -720,7 +720,8 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
            qemu_log_mask(LOG_GUEST_ERROR, "MPU_CTRL: HFNMIENA and !ENABLE is "

                          "UNPREDICTABLE\n");

        }

        cpu->env.v7m.mpu_ctrl = value & (R_V7M_MPU_CTRL_ENABLE_MASK |

        cpu->env.v7m.mpu_ctrl[attrs.secure]

            = value & (R_V7M_MPU_CTRL_ENABLE_MASK |

                       R_V7M_MPU_CTRL_HFNMIENA_MASK |

                       R_V7M_MPU_CTRL_PRIVDEFENA_MASK);

        tlb_flush(CPU(cpu));

target/arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -429,7 +429,7 @@ typedef struct CPUARMState { 
        uint32_t dfsr; /* Debug Fault Status Register */

        uint32_t mmfar; /* MemManage Fault Address */

        uint32_t bfar; /* BusFault Address */

        unsigned mpu_ctrl; /* MPU_CTRL */

        unsigned mpu_ctrl[2]; /* MPU_CTRL */

        int exception;

        uint32_t primask[2];

        uint32_t faultmask[2];

target/arm/helper.c

+3 −2
Original line number Diff line number Diff line
@@ -7091,7 +7091,7 @@ static inline bool regime_translation_disabled(CPUARMState *env, 
                                               ARMMMUIdx mmu_idx)

{

    if (arm_feature(env, ARM_FEATURE_M)) {

        switch (env->v7m.mpu_ctrl &

        switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &

                (R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {

        case R_V7M_MPU_CTRL_ENABLE_MASK:

            /* Enabled, but not for HardFault and NMI */
@@ -8251,7 +8251,8 @@ static bool pmsav7_use_background_region(ARMCPU *cpu, 
    }



    if (arm_feature(env, ARM_FEATURE_M)) {

        return env->v7m.mpu_ctrl & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;

        return env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)]

            & R_V7M_MPU_CTRL_PRIVDEFENA_MASK;

    } else {

        return regime_sctlr(env, mmu_idx) & SCTLR_BR;

    }

target/arm/machine.c

+2 −1
Original line number Diff line number Diff line
@@ -123,7 +123,7 @@ static const VMStateDescription vmstate_m = { 
        VMSTATE_UINT32(env.v7m.dfsr, ARMCPU),

        VMSTATE_UINT32(env.v7m.mmfar, ARMCPU),

        VMSTATE_UINT32(env.v7m.bfar, ARMCPU),

        VMSTATE_UINT32(env.v7m.mpu_ctrl, ARMCPU),

        VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_NS], ARMCPU),

        VMSTATE_INT32(env.v7m.exception, ARMCPU),

        VMSTATE_END_OF_LIST()

    },
@@ -270,6 +270,7 @@ static const VMStateDescription vmstate_m_security = { 
                              0, vmstate_info_uint32, uint32_t),

        VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),

        VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),

        VMSTATE_UINT32(env.v7m.mpu_ctrl[M_REG_S], ARMCPU),

        VMSTATE_END_OF_LIST()

    }

};