Commit 1bc04a88 authored by Peter Maydell's avatar Peter Maydell
Browse files

target/arm: Make MPU_RNR register banked for v8M 



Make the MPU_RNR register banked if v8M security extensions are
enabled.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 1503414539-28762-15-git-send-email-peter.maydell@linaro.org
parent 62c58ee0

hw/intc/armv7m_nvic.c

+9 −9
Original line number Diff line number Diff line
@@ -543,13 +543,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 
    case 0xd94: /* MPU_CTRL */

        return cpu->env.v7m.mpu_ctrl;

    case 0xd98: /* MPU_RNR */

        return cpu->env.pmsav7.rnr;

        return cpu->env.pmsav7.rnr[attrs.secure];

    case 0xd9c: /* MPU_RBAR */

    case 0xda4: /* MPU_RBAR_A1 */

    case 0xdac: /* MPU_RBAR_A2 */

    case 0xdb4: /* MPU_RBAR_A3 */

    {

        int region = cpu->env.pmsav7.rnr;

        int region = cpu->env.pmsav7.rnr[attrs.secure];



        if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {

            /* PMSAv8M handling of the aliases is different from v7M:
@@ -577,7 +577,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) 
    case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */

    case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */

    {

        int region = cpu->env.pmsav7.rnr;

        int region = cpu->env.pmsav7.rnr[attrs.secure];



        if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {

            /* PMSAv8M handling of the aliases is different from v7M:
@@ -731,7 +731,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
                          PRIu32 "/%" PRIu32 "\n",

                          value, cpu->pmsav7_dregion);

        } else {

            cpu->env.pmsav7.rnr = value;

            cpu->env.pmsav7.rnr[attrs.secure] = value;

        }

        break;

    case 0xd9c: /* MPU_RBAR */
@@ -749,7 +749,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
             */

            int aliasno = (offset - 0xd9c) / 8; /* 0..3 */



            region = cpu->env.pmsav7.rnr;

            region = cpu->env.pmsav7.rnr[attrs.secure];

            if (aliasno) {

                region = deposit32(region, 0, 2, aliasno);

            }
@@ -772,9 +772,9 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
                              region, cpu->pmsav7_dregion);

                return;

            }

            cpu->env.pmsav7.rnr = region;

            cpu->env.pmsav7.rnr[attrs.secure] = region;

        } else {

            region = cpu->env.pmsav7.rnr;

            region = cpu->env.pmsav7.rnr[attrs.secure];

        }



        if (region >= cpu->pmsav7_dregion) {
@@ -790,7 +790,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
    case 0xdb0: /* MPU_RASR_A2 (v7M), MPU_RLAR_A2 (v8M) */

    case 0xdb8: /* MPU_RASR_A3 (v7M), MPU_RLAR_A3 (v8M) */

    {

        int region = cpu->env.pmsav7.rnr;

        int region = cpu->env.pmsav7.rnr[attrs.secure];



        if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {

            /* PMSAv8M handling of the aliases is different from v7M:
@@ -799,7 +799,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, 
             */

            int aliasno = (offset - 0xd9c) / 8; /* 0..3 */



            region = cpu->env.pmsav7.rnr;

            region = cpu->env.pmsav7.rnr[attrs.secure];

            if (aliasno) {

                region = deposit32(region, 0, 2, aliasno);

            }

target/arm/cpu.c

+2 −1
Original line number Diff line number Diff line
@@ -258,7 +258,8 @@ static void arm_cpu_reset(CPUState *s) 
                       sizeof(*env->pmsav7.dracr) * cpu->pmsav7_dregion);

            }

        }

        env->pmsav7.rnr = 0;

        env->pmsav7.rnr[M_REG_NS] = 0;

        env->pmsav7.rnr[M_REG_S] = 0;

        env->pmsav8.mair0[M_REG_NS] = 0;

        env->pmsav8.mair0[M_REG_S] = 0;

        env->pmsav8.mair1[M_REG_NS] = 0;

target/arm/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -533,7 +533,7 @@ typedef struct CPUARMState { 
        uint32_t *drbar;

        uint32_t *drsr;

        uint32_t *dracr;

        uint32_t rnr;

        uint32_t rnr[2];

    } pmsav7;



    /* PMSAv8 MPU */

target/arm/helper.c

+3 −3
Original line number Diff line number Diff line
@@ -2385,7 +2385,7 @@ static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri) 
        return 0;

    }



    u32p += env->pmsav7.rnr;

    u32p += env->pmsav7.rnr[M_REG_NS];

    return *u32p;

}
@@ -2399,7 +2399,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri, 
        return;

    }



    u32p += env->pmsav7.rnr;

    u32p += env->pmsav7.rnr[M_REG_NS];

    tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */

    *u32p = value;

}
@@ -2442,7 +2442,7 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] = { 
      .resetfn = arm_cp_reset_ignore },

    { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,

      .access = PL1_RW,

      .fieldoffset = offsetof(CPUARMState, pmsav7.rnr),

      .fieldoffset = offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]),

      .writefn = pmsav7_rgnr_write,

      .resetfn = arm_cp_reset_ignore },

    REGINFO_SENTINEL

target/arm/machine.c

+11 −2
Original line number Diff line number Diff line
@@ -167,7 +167,7 @@ static bool pmsav7_rgnr_vmstate_validate(void *opaque, int version_id) 
{

    ARMCPU *cpu = opaque;



    return cpu->env.pmsav7.rnr < cpu->pmsav7_dregion;

    return cpu->env.pmsav7.rnr[M_REG_NS] < cpu->pmsav7_dregion;

}



static const VMStateDescription vmstate_pmsav7 = {
@@ -205,7 +205,7 @@ static const VMStateDescription vmstate_pmsav7_rnr = { 
    .minimum_version_id = 1,

    .needed = pmsav7_rnr_needed,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(env.pmsav7.rnr, ARMCPU),

        VMSTATE_UINT32(env.pmsav7.rnr[M_REG_NS], ARMCPU),

        VMSTATE_END_OF_LIST()

    }

};
@@ -235,6 +235,13 @@ static const VMStateDescription vmstate_pmsav8 = { 
    }

};



static bool s_rnr_vmstate_validate(void *opaque, int version_id)

{

    ARMCPU *cpu = opaque;



    return cpu->env.pmsav7.rnr[M_REG_S] < cpu->pmsav7_dregion;

}



static bool m_security_needed(void *opaque)

{

    ARMCPU *cpu = opaque;
@@ -261,6 +268,8 @@ static const VMStateDescription vmstate_m_security = { 
                              0, vmstate_info_uint32, uint32_t),

        VMSTATE_VARRAY_UINT32(env.pmsav8.rlar[M_REG_S], ARMCPU, pmsav7_dregion,

                              0, vmstate_info_uint32, uint32_t),

        VMSTATE_UINT32(env.pmsav7.rnr[M_REG_S], ARMCPU),

        VMSTATE_VALIDATE("secure MPU_RNR is valid", s_rnr_vmstate_validate),

        VMSTATE_END_OF_LIST()

    }

};