Unverified Commit e44b50b5 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
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target/riscv: Add the MSTATUS_MPV_ISSET helper macro 



Add a helper macro MSTATUS_MPV_ISSET() which will determine if the
MSTATUS_MPV bit is set for both 32-bit and 64-bit RISC-V.

Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 551fa7e8

target/riscv/cpu_bits.h

+11 −0
Original line number Diff line number Diff line
@@ -363,8 +363,19 @@ 
#define MSTATUS_TVM         0x00100000 /* since: priv-1.10 */

#define MSTATUS_TW          0x20000000 /* since: priv-1.10 */

#define MSTATUS_TSR         0x40000000 /* since: priv-1.10 */

#if defined(TARGET_RISCV64)

#define MSTATUS_MTL         0x4000000000ULL

#define MSTATUS_MPV         0x8000000000ULL

#elif defined(TARGET_RISCV32)

#define MSTATUS_MTL         0x00000040

#define MSTATUS_MPV         0x00000080

#endif



#ifdef TARGET_RISCV32

# define MSTATUS_MPV_ISSET(env)  get_field(env->mstatush, MSTATUS_MPV)

#else

# define MSTATUS_MPV_ISSET(env)  get_field(env->mstatus, MSTATUS_MPV)

#endif



#define MSTATUS64_UXL       0x0000000300000000ULL

#define MSTATUS64_SXL       0x0000000C00000000ULL

target/riscv/cpu_helper.c

+2 −2
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, 
            mode = get_field(env->mstatus, MSTATUS_MPP);



            if (riscv_has_ext(env, RVH) &&

                get_field(env->mstatus, MSTATUS_MPV)) {

                MSTATUS_MPV_ISSET(env)) {

                use_background = true;

            }

        }
@@ -722,7 +722,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 
        m_mode_two_stage = env->priv == PRV_M &&

                           access_type != MMU_INST_FETCH &&

                           get_field(env->mstatus, MSTATUS_MPRV) &&

                           get_field(env->mstatus, MSTATUS_MPV);

                           MSTATUS_MPV_ISSET(env);



        hs_mode_two_stage = env->priv == PRV_S &&

                            !riscv_cpu_virt_enabled(env) &&

target/riscv/op_helper.c

+1 −1
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) 


    target_ulong mstatus = env->mstatus;

    target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP);

    target_ulong prev_virt = get_field(mstatus, MSTATUS_MPV);

    target_ulong prev_virt = MSTATUS_MPV_ISSET(env);

    mstatus = set_field(mstatus,

        env->priv_ver >= PRIV_VERSION_1_10_0 ?

        MSTATUS_MIE : MSTATUS_UIE << prev_priv,

target/riscv/translate.c

+1 −1
Original line number Diff line number Diff line
@@ -755,7 +755,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 
        ctx->virt_enabled = riscv_cpu_virt_enabled(env);

        if (env->priv_ver == PRV_M &&

            get_field(env->mstatus, MSTATUS_MPRV) &&

            get_field(env->mstatus, MSTATUS_MPV)) {

            MSTATUS_MPV_ISSET(env)) {

            ctx->virt_enabled = true;

        } else if (env->priv == PRV_S &&

                   !riscv_cpu_virt_enabled(env) &&