Unverified Commit 551fa7e8 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
Browse files

target/riscv: Add support for the 32-bit MSTATUSH CSR 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent 30675539

target/riscv/cpu.c

+3 −0
Original line number Diff line number Diff line
@@ -237,6 +237,9 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 
#ifndef CONFIG_USER_ONLY

    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);

    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);

#ifdef TARGET_RISCV32

    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);

#endif

    if (riscv_has_ext(env, RVH)) {

        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);

        qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);

target/riscv/cpu.h

+10 −0
Original line number Diff line number Diff line
@@ -127,6 +127,10 @@ struct CPURISCVState { 


    target_ulong mip;



#ifdef TARGET_RISCV32

    target_ulong mstatush;

#endif



    uint32_t miclaim;



    target_ulong mie;
@@ -164,6 +168,9 @@ struct CPURISCVState { 
    target_ulong vscause;

    target_ulong vstval;

    target_ulong vsatp;

#ifdef TARGET_RISCV32

    target_ulong vsstatush;

#endif



    target_ulong mtval2;

    target_ulong mtinst;
@@ -176,6 +183,9 @@ struct CPURISCVState { 
    target_ulong stval_hs;

    target_ulong satp_hs;

    target_ulong mstatus_hs;

#ifdef TARGET_RISCV32

    target_ulong mstatush_hs;

#endif



    target_ulong scounteren;

    target_ulong mcounteren;

target/riscv/cpu_bits.h

+3 −0
Original line number Diff line number Diff line
@@ -135,6 +135,9 @@ 
#define CSR_MTVEC           0x305

#define CSR_MCOUNTEREN      0x306



/* 32-bit only */

#define CSR_MSTATUSH        0x310



/* Legacy Counter Setup (priv v1.9.1) */

/* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */

#define CSR_MUCOUNTEREN     0x320

target/riscv/cpu_helper.c

+17 −0
Original line number Diff line number Diff line
@@ -126,6 +126,11 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 
        env->mstatus &= ~mstatus_mask;

        env->mstatus |= env->mstatus_hs;



#if defined(TARGET_RISCV32)

        env->vsstatush = env->mstatush;

        env->mstatush |= env->mstatush_hs;

#endif



        env->vstvec = env->stvec;

        env->stvec = env->stvec_hs;
@@ -149,6 +154,11 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) 
        env->mstatus &= ~mstatus_mask;

        env->mstatus |= env->vsstatus;



#if defined(TARGET_RISCV32)

        env->mstatush_hs = env->mstatush;

        env->mstatush |= env->vsstatush;

#endif



        env->stvec_hs = env->stvec;

        env->stvec = env->vstvec;
@@ -939,10 +949,17 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
            if (riscv_cpu_virt_enabled(env)) {

                riscv_cpu_swap_hypervisor_regs(env);

            }

#ifdef TARGET_RISCV32

            env->mstatush = set_field(env->mstatush, MSTATUS_MPV,

                                       riscv_cpu_virt_enabled(env));

            env->mstatush = set_field(env->mstatush, MSTATUS_MTL,

                                       riscv_cpu_force_hs_excep_enabled(env));

#else

            env->mstatus = set_field(env->mstatus, MSTATUS_MPV,

                                      riscv_cpu_virt_enabled(env));

            env->mstatus = set_field(env->mstatus, MSTATUS_MTL,

                                      riscv_cpu_force_hs_excep_enabled(env));

#endif



            mtval2 = env->guest_phys_fault_addr;

target/riscv/csr.c

+25 −0
Original line number Diff line number Diff line
@@ -371,6 +371,27 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) 
    return 0;

}



#ifdef TARGET_RISCV32

static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)

{

    *val = env->mstatush;

    return 0;

}



static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)

{

    if ((val ^ env->mstatush) & (MSTATUS_MPV)) {

        tlb_flush(env_cpu(env));

    }



    val &= MSTATUS_MPV | MSTATUS_MTL;



    env->mstatush = val;



    return 0;

}

#endif



static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)

{

    *val = env->misa;
@@ -1214,6 +1235,10 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { 
    [CSR_MTVEC] =               { any,  read_mtvec,       write_mtvec       },

    [CSR_MCOUNTEREN] =          { any,  read_mcounteren,  write_mcounteren  },



#if defined(TARGET_RISCV32)

    [CSR_MSTATUSH] =            { any,  read_mstatush,    write_mstatush    },

#endif



    /* Legacy Counter Setup (priv v1.9.1) */

    [CSR_MUCOUNTEREN] =         { any,  read_mucounteren, write_mucounteren },

    [CSR_MSCOUNTEREN] =         { any,  read_mscounteren, write_mscounteren },