Unverified Commit 30675539 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
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target/riscv: Set htval and mtval2 on execptions 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent b2ef6ab9

target/riscv/cpu_helper.c

+10 −0
Original line number Diff line number Diff line
@@ -840,6 +840,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
    target_ulong cause = cs->exception_index & RISCV_EXCP_INT_MASK;

    target_ulong deleg = async ? env->mideleg : env->medeleg;

    target_ulong tval = 0;

    target_ulong htval = 0;

    target_ulong mtval2 = 0;



    if (!async) {

        /* set tval to badaddr for traps with address information */
@@ -901,6 +903,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,

                                         riscv_cpu_virt_enabled(env));



                htval = env->guest_phys_fault_addr;



                riscv_cpu_set_virt_enabled(env, 0);

                riscv_cpu_set_force_hs_excep(env, 0);

            } else {
@@ -911,6 +915,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
                                         get_field(env->mstatus, SSTATUS_SPP));

                env->hstatus = set_field(env->hstatus, HSTATUS_SPV,

                                         riscv_cpu_virt_enabled(env));



                htval = env->guest_phys_fault_addr;

            }

        }
@@ -923,6 +929,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
        env->scause = cause | ((target_ulong)async << (TARGET_LONG_BITS - 1));

        env->sepc = env->pc;

        env->sbadaddr = tval;

        env->htval = htval;

        env->pc = (env->stvec >> 2 << 2) +

            ((async && (env->stvec & 3) == 1) ? cause * 4 : 0);

        riscv_cpu_set_mode(env, PRV_S);
@@ -937,6 +944,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
            env->mstatus = set_field(env->mstatus, MSTATUS_MTL,

                                      riscv_cpu_force_hs_excep_enabled(env));



            mtval2 = env->guest_phys_fault_addr;



            /* Trapping to M mode, virt is disabled */

            riscv_cpu_set_virt_enabled(env, 0);

            riscv_cpu_set_force_hs_excep(env, 0);
@@ -951,6 +960,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) 
        env->mcause = cause | ~(((target_ulong)-1) >> async);

        env->mepc = env->pc;

        env->mbadaddr = tval;

        env->mtval2 = mtval2;

        env->pc = (env->mtvec >> 2 << 2) +

            ((async && (env->mtvec & 3) == 1) ? cause * 4 : 0);

        riscv_cpu_set_mode(env, PRV_M);