Commit e2684c0b authored by Andreas Färber's avatar Andreas Färber
Browse files

ppc hw/: Don't use CPUState 



Scripted conversion:
  for file in hw/ppc*.[hc] hw/mpc8544_guts.c hw/spapr*.[hc] hw/virtex_ml507.c hw/xics.c; do
    sed -i "s/CPUState/CPUPPCState/g" $file
  done

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
Acked-by: default avatarAnthony Liguori <aliguori@us.ibm.com>
parent 61c56c8c

hw/mpc8544_guts.c

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static uint64_t mpc8544_guts_read(void *opaque, target_phys_addr_t addr, 
                                  unsigned size)

{

    uint32_t value = 0;

    CPUState *env = cpu_single_env;

    CPUPPCState *env = cpu_single_env;



    addr &= MPC8544_GUTS_MMIO_SIZE - 1;

    switch (addr) {

hw/ppc.c

+55 −55
Original line number Diff line number Diff line
@@ -47,10 +47,10 @@ 
#  define LOG_TB(...) do { } while (0)

#endif



static void cpu_ppc_tb_stop (CPUState *env);

static void cpu_ppc_tb_start (CPUState *env);

static void cpu_ppc_tb_stop (CPUPPCState *env);

static void cpu_ppc_tb_start (CPUPPCState *env);



void ppc_set_irq(CPUState *env, int n_IRQ, int level)

void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level)

{

    unsigned int old_pending = env->pending_interrupts;
@@ -77,7 +77,7 @@ void ppc_set_irq(CPUState *env, int n_IRQ, int level) 
/* PowerPC 6xx / 7xx internal IRQ controller */

static void ppc6xx_set_irq (void *opaque, int pin, int level)

{

    CPUState *env = opaque;

    CPUPPCState *env = opaque;

    int cur_level;



    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -151,7 +151,7 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) 
    }

}



void ppc6xx_irq_init (CPUState *env)

void ppc6xx_irq_init (CPUPPCState *env)

{

    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,

                                                  PPC6xx_INPUT_NB);
@@ -161,7 +161,7 @@ void ppc6xx_irq_init (CPUState *env) 
/* PowerPC 970 internal IRQ controller */

static void ppc970_set_irq (void *opaque, int pin, int level)

{

    CPUState *env = opaque;

    CPUPPCState *env = opaque;

    int cur_level;



    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -233,7 +233,7 @@ static void ppc970_set_irq (void *opaque, int pin, int level) 
    }

}



void ppc970_irq_init (CPUState *env)

void ppc970_irq_init (CPUPPCState *env)

{

    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,

                                                  PPC970_INPUT_NB);
@@ -242,7 +242,7 @@ void ppc970_irq_init (CPUState *env) 
/* POWER7 internal IRQ controller */

static void power7_set_irq (void *opaque, int pin, int level)

{

    CPUState *env = opaque;

    CPUPPCState *env = opaque;



    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,

                env, pin, level);
@@ -266,7 +266,7 @@ static void power7_set_irq (void *opaque, int pin, int level) 
    }

}



void ppcPOWER7_irq_init (CPUState *env)

void ppcPOWER7_irq_init (CPUPPCState *env)

{

    env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env,

                                                  POWER7_INPUT_NB);
@@ -276,7 +276,7 @@ void ppcPOWER7_irq_init (CPUState *env) 
/* PowerPC 40x internal IRQ controller */

static void ppc40x_set_irq (void *opaque, int pin, int level)

{

    CPUState *env = opaque;

    CPUPPCState *env = opaque;

    int cur_level;



    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -346,7 +346,7 @@ static void ppc40x_set_irq (void *opaque, int pin, int level) 
    }

}



void ppc40x_irq_init (CPUState *env)

void ppc40x_irq_init (CPUPPCState *env)

{

    env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,

                                                  env, PPC40x_INPUT_NB);
@@ -355,7 +355,7 @@ void ppc40x_irq_init (CPUState *env) 
/* PowerPC E500 internal IRQ controller */

static void ppce500_set_irq (void *opaque, int pin, int level)

{

    CPUState *env = opaque;

    CPUPPCState *env = opaque;

    int cur_level;



    LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
@@ -407,7 +407,7 @@ static void ppce500_set_irq (void *opaque, int pin, int level) 
    }

}



void ppce500_irq_init (CPUState *env)

void ppce500_irq_init (CPUPPCState *env)

{

    env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,

                                        env, PPCE500_INPUT_NB);
@@ -421,7 +421,7 @@ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 
    return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;

}



uint64_t cpu_ppc_load_tbl (CPUState *env)

uint64_t cpu_ppc_load_tbl (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -436,7 +436,7 @@ uint64_t cpu_ppc_load_tbl (CPUState *env) 
    return tb;

}



static inline uint32_t _cpu_ppc_load_tbu(CPUState *env)

static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -447,7 +447,7 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) 
    return tb >> 32;

}



uint32_t cpu_ppc_load_tbu (CPUState *env)

uint32_t cpu_ppc_load_tbu (CPUPPCState *env)

{

    if (kvm_enabled()) {

        return env->spr[SPR_TBU];
@@ -464,7 +464,7 @@ static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 
                __func__, value, *tb_offsetp);

}



void cpu_ppc_store_tbl (CPUState *env, uint32_t value)

void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -475,7 +475,7 @@ void cpu_ppc_store_tbl (CPUState *env, uint32_t value) 
                     &tb_env->tb_offset, tb | (uint64_t)value);

}



static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value)

static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -486,12 +486,12 @@ static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) 
                     &tb_env->tb_offset, ((uint64_t)value << 32) | tb);

}



void cpu_ppc_store_tbu (CPUState *env, uint32_t value)

void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value)

{

    _cpu_ppc_store_tbu(env, value);

}



uint64_t cpu_ppc_load_atbl (CPUState *env)

uint64_t cpu_ppc_load_atbl (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -502,7 +502,7 @@ uint64_t cpu_ppc_load_atbl (CPUState *env) 
    return tb;

}



uint32_t cpu_ppc_load_atbu (CPUState *env)

uint32_t cpu_ppc_load_atbu (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -513,7 +513,7 @@ uint32_t cpu_ppc_load_atbu (CPUState *env) 
    return tb >> 32;

}



void cpu_ppc_store_atbl (CPUState *env, uint32_t value)

void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -524,7 +524,7 @@ void cpu_ppc_store_atbl (CPUState *env, uint32_t value) 
                     &tb_env->atb_offset, tb | (uint64_t)value);

}



void cpu_ppc_store_atbu (CPUState *env, uint32_t value)

void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb;
@@ -535,7 +535,7 @@ void cpu_ppc_store_atbu (CPUState *env, uint32_t value) 
                     &tb_env->atb_offset, ((uint64_t)value << 32) | tb);

}



static void cpu_ppc_tb_stop (CPUState *env)

static void cpu_ppc_tb_stop (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb, atb, vmclk;
@@ -557,7 +557,7 @@ static void cpu_ppc_tb_stop (CPUState *env) 
    }

}



static void cpu_ppc_tb_start (CPUState *env)

static void cpu_ppc_tb_start (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t tb, atb, vmclk;
@@ -578,7 +578,7 @@ static void cpu_ppc_tb_start (CPUState *env) 
    }

}



static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next)

static inline uint32_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint32_t decr;
@@ -597,7 +597,7 @@ static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) 
    return decr;

}



uint32_t cpu_ppc_load_decr (CPUState *env)

uint32_t cpu_ppc_load_decr (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;
@@ -608,14 +608,14 @@ uint32_t cpu_ppc_load_decr (CPUState *env) 
    return _cpu_ppc_load_decr(env, tb_env->decr_next);

}



uint32_t cpu_ppc_load_hdecr (CPUState *env)

uint32_t cpu_ppc_load_hdecr (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;



    return _cpu_ppc_load_decr(env, tb_env->hdecr_next);

}



uint64_t cpu_ppc_load_purr (CPUState *env)

uint64_t cpu_ppc_load_purr (CPUPPCState *env)

{

    ppc_tb_t *tb_env = env->tb_env;

    uint64_t diff;
@@ -628,23 +628,23 @@ uint64_t cpu_ppc_load_purr (CPUState *env) 
/* When decrementer expires,

 * all we need to do is generate or queue a CPU exception

 */

static inline void cpu_ppc_decr_excp(CPUState *env)

static inline void cpu_ppc_decr_excp(CPUPPCState *env)

{

    /* Raise it */

    LOG_TB("raise decrementer exception\n");

    ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);

}



static inline void cpu_ppc_hdecr_excp(CPUState *env)

static inline void cpu_ppc_hdecr_excp(CPUPPCState *env)

{

    /* Raise it */

    LOG_TB("raise decrementer exception\n");

    ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);

}



static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp,

static void __cpu_ppc_store_decr (CPUPPCState *env, uint64_t *nextp,

                                  struct QEMUTimer *timer,

                                  void (*raise_excp)(CPUState *),

                                  void (*raise_excp)(CPUPPCState *),

                                  uint32_t decr, uint32_t value,

                                  int is_excp)

{
@@ -681,7 +681,7 @@ static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, 
    }

}



static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr,

static inline void _cpu_ppc_store_decr(CPUPPCState *env, uint32_t decr,

                                       uint32_t value, int is_excp)

{

    ppc_tb_t *tb_env = env->tb_env;
@@ -690,7 +690,7 @@ static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, 
                         &cpu_ppc_decr_excp, decr, value, is_excp);

}



void cpu_ppc_store_decr (CPUState *env, uint32_t value)

void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value)

{

    _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);

}
@@ -700,7 +700,7 @@ static void cpu_ppc_decr_cb (void *opaque) 
    _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1);

}



static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr,

static inline void _cpu_ppc_store_hdecr(CPUPPCState *env, uint32_t hdecr,

                                        uint32_t value, int is_excp)

{

    ppc_tb_t *tb_env = env->tb_env;
@@ -711,7 +711,7 @@ static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, 
    }

}



void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)

void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value)

{

    _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);

}
@@ -721,7 +721,7 @@ static void cpu_ppc_hdecr_cb (void *opaque) 
    _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1);

}



void cpu_ppc_store_purr (CPUState *env, uint64_t value)

void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value)

{

    ppc_tb_t *tb_env = env->tb_env;
@@ -731,7 +731,7 @@ void cpu_ppc_store_purr (CPUState *env, uint64_t value) 


static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq)

{

    CPUState *env = opaque;

    CPUPPCState *env = opaque;

    ppc_tb_t *tb_env = env->tb_env;



    tb_env->tb_freq = freq;
@@ -746,7 +746,7 @@ static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 
}



/* Set up (once) timebase frequency (in Hz) */

clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq)

clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)

{

    ppc_tb_t *tb_env;
@@ -769,28 +769,28 @@ clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) 


/* Specific helpers for POWER & PowerPC 601 RTC */

#if 0

static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)

static clk_setup_cb cpu_ppc601_rtc_init (CPUPPCState *env)

{

    return cpu_ppc_tb_init(env, 7812500);

}

#endif



void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)

void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value)

{

    _cpu_ppc_store_tbu(env, value);

}



uint32_t cpu_ppc601_load_rtcu (CPUState *env)

uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env)

{

    return _cpu_ppc_load_tbu(env);

}



void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)

void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value)

{

    cpu_ppc_store_tbl(env, value & 0x3FFFFF80);

}



uint32_t cpu_ppc601_load_rtcl (CPUState *env)

uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env)

{

    return cpu_ppc_load_tbl(env) & 0x3FFFFF80;

}
@@ -814,7 +814,7 @@ struct ppc40x_timer_t { 
/* Fixed interval timer */

static void cpu_4xx_fit_cb (void *opaque)

{

    CPUState *env;

    CPUPPCState *env;

    ppc_tb_t *tb_env;

    ppc40x_timer_t *ppc40x_timer;

    uint64_t now, next;
@@ -853,7 +853,7 @@ static void cpu_4xx_fit_cb (void *opaque) 
}



/* Programmable interval timer */

static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp)

static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp)

{

    ppc40x_timer_t *ppc40x_timer;

    uint64_t now, next;
@@ -882,7 +882,7 @@ static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) 


static void cpu_4xx_pit_cb (void *opaque)

{

    CPUState *env;

    CPUPPCState *env;

    ppc_tb_t *tb_env;

    ppc40x_timer_t *ppc40x_timer;
@@ -904,7 +904,7 @@ static void cpu_4xx_pit_cb (void *opaque) 
/* Watchdog timer */

static void cpu_4xx_wdt_cb (void *opaque)

{

    CPUState *env;

    CPUPPCState *env;

    ppc_tb_t *tb_env;

    ppc40x_timer_t *ppc40x_timer;

    uint64_t now, next;
@@ -969,7 +969,7 @@ static void cpu_4xx_wdt_cb (void *opaque) 
    }

}



void store_40x_pit (CPUState *env, target_ulong val)

void store_40x_pit (CPUPPCState *env, target_ulong val)

{

    ppc_tb_t *tb_env;

    ppc40x_timer_t *ppc40x_timer;
@@ -981,14 +981,14 @@ void store_40x_pit (CPUState *env, target_ulong val) 
    start_stop_pit(env, tb_env, 0);

}



target_ulong load_40x_pit (CPUState *env)

target_ulong load_40x_pit (CPUPPCState *env)

{

    return cpu_ppc_load_decr(env);

}



static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq)

{

    CPUState *env = opaque;

    CPUPPCState *env = opaque;

    ppc_tb_t *tb_env = env->tb_env;



    LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__,
@@ -998,7 +998,7 @@ static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 
    /* XXX: we should also update all timers */

}



clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,

clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,

                                  unsigned int decr_excp)

{

    ppc_tb_t *tb_env;
@@ -1084,7 +1084,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 
    return -1;

}



int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,

int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,

                      dcr_read_cb dcr_read, dcr_write_cb dcr_write)

{

    ppc_dcr_t *dcr_env;
@@ -1107,7 +1107,7 @@ int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, 
    return 0;

}



int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn),

int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn),

                  int (*write_error)(int dcrn))

{

    ppc_dcr_t *dcr_env;

hw/ppc.h

+14 −14
Original line number Diff line number Diff line 
void ppc_set_irq (CPUState *env, int n_IRQ, int level);

void ppc_set_irq (CPUPPCState *env, int n_IRQ, int level);



/* PowerPC hardware exceptions management helpers */

typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
@@ -43,32 +43,32 @@ struct ppc_tb_t { 
                                               */



uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);

clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);

clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);

/* Embedded PowerPC DCR management */

typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);

typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);

int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),

int ppc_dcr_init (CPUPPCState *env, int (*dcr_read_error)(int dcrn),

                  int (*dcr_write_error)(int dcrn));

int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,

int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque,

                      dcr_read_cb drc_read, dcr_write_cb dcr_write);

clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq,

clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq,

                                  unsigned int decr_excp);



/* Embedded PowerPC reset */

void ppc40x_core_reset (CPUState *env);

void ppc40x_chip_reset (CPUState *env);

void ppc40x_system_reset (CPUState *env);

void ppc40x_core_reset (CPUPPCState *env);

void ppc40x_chip_reset (CPUPPCState *env);

void ppc40x_system_reset (CPUPPCState *env);

void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);



extern CPUWriteMemoryFunc * const PPC_io_write[];

extern CPUReadMemoryFunc * const PPC_io_read[];

void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);



void ppc40x_irq_init (CPUState *env);

void ppce500_irq_init (CPUState *env);

void ppc6xx_irq_init (CPUState *env);

void ppc970_irq_init (CPUState *env);

void ppcPOWER7_irq_init (CPUState *env);

void ppc40x_irq_init (CPUPPCState *env);

void ppce500_irq_init (CPUPPCState *env);

void ppc6xx_irq_init (CPUPPCState *env);

void ppc970_irq_init (CPUPPCState *env);

void ppcPOWER7_irq_init (CPUPPCState *env);



/* PPC machines for OpenBIOS */

enum {
@@ -89,4 +89,4 @@ enum { 
#define PPC_SERIAL_MM_BAUDBASE 399193



/* ppc_booke.c */

void ppc_booke_timers_init(CPUState *env, uint32_t freq, uint32_t flags);
 
void ppc_booke_timers_init(CPUPPCState *env, uint32_t freq, uint32_t flags);

hw/ppc405.h

+4 −4
Original line number Diff line number Diff line
@@ -56,23 +56,23 @@ struct ppc4xx_bd_info_t { 
};



/* PowerPC 405 core */

ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,

ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,

                                uint32_t flags);



CPUState *ppc405cr_init(MemoryRegion *address_space_mem,

CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,

                        MemoryRegion ram_memories[4],

                        target_phys_addr_t ram_bases[4],

                        target_phys_addr_t ram_sizes[4],

                        uint32_t sysclk, qemu_irq **picp,

                        int do_init);

CPUState *ppc405ep_init(MemoryRegion *address_space_mem,

CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,

                        MemoryRegion ram_memories[2],

                        target_phys_addr_t ram_bases[2],

                        target_phys_addr_t ram_sizes[2],

                        uint32_t sysclk, qemu_irq **picp,

                        int do_init);

/* IBM STBxxx microcontrollers */

CPUState *ppc_stb025_init (MemoryRegion ram_memories[2],

CPUPPCState *ppc_stb025_init (MemoryRegion ram_memories[2],

                           target_phys_addr_t ram_bases[2],

                           target_phys_addr_t ram_sizes[2],

                           uint32_t sysclk, qemu_irq **picp,

hw/ppc405_uc.c

+17 −17
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ 
#define DEBUG_CLOCKS

//#define DEBUG_CLOCKS_LL



ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd,

ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,

                                uint32_t flags)

{

    ram_addr_t bdloc;
@@ -169,7 +169,7 @@ static void ppc4xx_plb_reset (void *opaque) 
    plb->besr = 0x00000000;

}



static void ppc4xx_plb_init(CPUState *env)

static void ppc4xx_plb_init(CPUPPCState *env)

{

    ppc4xx_plb_t *plb;
@@ -245,7 +245,7 @@ static void ppc4xx_pob_reset (void *opaque) 
    pob->besr[1] = 0x0000000;

}



static void ppc4xx_pob_init(CPUState *env)

static void ppc4xx_pob_init(CPUPPCState *env)

{

    ppc4xx_pob_t *pob;
@@ -574,7 +574,7 @@ static void ebc_reset (void *opaque) 
    ebc->cfg = 0x80400000;

}



static void ppc405_ebc_init(CPUState *env)

static void ppc405_ebc_init(CPUPPCState *env)

{

    ppc4xx_ebc_t *ebc;
@@ -657,7 +657,7 @@ static void ppc405_dma_reset (void *opaque) 
    dma->pol = 0x00000000;

}



static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])

static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])

{

    ppc405_dma_t *dma;
@@ -960,7 +960,7 @@ static void ocm_reset (void *opaque) 
    ocm->dsacntl = dsacntl;

}



static void ppc405_ocm_init(CPUState *env)

static void ppc405_ocm_init(CPUPPCState *env)

{

    ppc405_ocm_t *ocm;
@@ -1713,7 +1713,7 @@ static void ppc40x_mal_reset (void *opaque) 
    mal->txeobisr = 0x00000000;

}



static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])

static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])

{

    ppc40x_mal_t *mal;

    int i;
@@ -1764,7 +1764,7 @@ static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4]) 


/*****************************************************************************/

/* SPR */

void ppc40x_core_reset (CPUState *env)

void ppc40x_core_reset (CPUPPCState *env)

{

    target_ulong dbsr;
@@ -1776,7 +1776,7 @@ void ppc40x_core_reset (CPUState *env) 
    env->spr[SPR_40x_DBSR] = dbsr;

}



void ppc40x_chip_reset (CPUState *env)

void ppc40x_chip_reset (CPUPPCState *env)

{

    target_ulong dbsr;
@@ -1789,13 +1789,13 @@ void ppc40x_chip_reset (CPUState *env) 
    env->spr[SPR_40x_DBSR] = dbsr;

}



void ppc40x_system_reset (CPUState *env)

void ppc40x_system_reset (CPUPPCState *env)

{

    printf("Reset PowerPC system\n");

    qemu_system_reset_request();

}



void store_40x_dbcr0 (CPUState *env, uint32_t val)

void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)

{

    switch ((val >> 28) & 0x3) {

    case 0x0:
@@ -2066,7 +2066,7 @@ static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc) 
    cpc->psr |= D << 17;

}



static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],

static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],

                               uint32_t sysclk)

{

    ppc405cr_cpc_t *cpc;
@@ -2096,7 +2096,7 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], 
    qemu_register_reset(ppc405cr_cpc_reset, cpc);

}



CPUState *ppc405cr_init(MemoryRegion *address_space_mem,

CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,

                        MemoryRegion ram_memories[4],

                        target_phys_addr_t ram_bases[4],

                        target_phys_addr_t ram_sizes[4],
@@ -2105,7 +2105,7 @@ CPUState *ppc405cr_init(MemoryRegion *address_space_mem, 
{

    clk_setup_t clk_setup[PPC405CR_CLK_NB];

    qemu_irq dma_irqs[4];

    CPUState *env;

    CPUPPCState *env;

    qemu_irq *pic, *irqs;



    memset(clk_setup, 0, sizeof(clk_setup));
@@ -2408,7 +2408,7 @@ static void ppc405ep_cpc_reset (void *opaque) 
}



/* XXX: sysclk should be between 25 and 100 MHz */

static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],

static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],

                               uint32_t sysclk)

{

    ppc405ep_cpc_t *cpc;
@@ -2445,7 +2445,7 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], 
#endif

}



CPUState *ppc405ep_init(MemoryRegion *address_space_mem,

CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,

                        MemoryRegion ram_memories[2],

                        target_phys_addr_t ram_bases[2],

                        target_phys_addr_t ram_sizes[2],
@@ -2454,7 +2454,7 @@ CPUState *ppc405ep_init(MemoryRegion *address_space_mem, 
{

    clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;

    qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];

    CPUState *env;

    CPUPPCState *env;

    qemu_irq *pic, *irqs;



    memset(clk_setup, 0, sizeof(clk_setup));