Unverified Commit e0643110 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
Browse files

target/riscv: Add the HGATP register masks 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent d28b15a4

target/riscv/cpu_bits.h

+11 −0
Original line number Diff line number Diff line
@@ -208,6 +208,17 @@ 
#define CSR_HIDELEG         0xa03

#define CSR_HGATP           0xa80



#if defined(TARGET_RISCV32)

#define HGATP_MODE           SATP32_MODE

#define HGATP_ASID           SATP32_ASID

#define HGATP_PPN            SATP32_PPN

#endif

#if defined(TARGET_RISCV64)

#define HGATP_MODE           SATP64_MODE

#define HGATP_ASID           SATP64_ASID

#define HGATP_PPN            SATP64_PPN

#endif



/* Performance Counters */

#define CSR_MHPMCOUNTER3    0xb03

#define CSR_MHPMCOUNTER4    0xb04