Unverified Commit d28b15a4 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
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target/riscv: Add the HSTATUS register masks 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviwed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmer@sifive.com>
parent 71f09a5b

target/riscv/cpu_bits.h

+18 −0
Original line number Diff line number Diff line
@@ -382,6 +382,24 @@ 
#define SSTATUS_SD SSTATUS64_SD

#endif



/* hstatus CSR bits */

#define HSTATUS_SPRV         0x00000001

#define HSTATUS_STL          0x00000040

#define HSTATUS_SPV          0x00000080

#define HSTATUS_SP2P         0x00000100

#define HSTATUS_SP2V         0x00000200

#define HSTATUS_VTVM         0x00100000

#define HSTATUS_VTSR         0x00400000



#define HSTATUS32_WPRI       0xFF8FF87E

#define HSTATUS64_WPRI       0xFFFFFFFFFF8FF87EULL



#if defined(TARGET_RISCV32)

#define HSTATUS_WPRI HSTATUS32_WPRI

#elif defined(TARGET_RISCV64)

#define HSTATUS_WPRI HSTATUS64_WPRI

#endif



/* Privilege modes */

#define PRV_U 0

#define PRV_S 1