Commit dc7abe4d authored by Michael Davidsaver's avatar Michael Davidsaver Committed by Peter Maydell
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armv7m: FAULTMASK should be 0 on reset



For M profile CPUs, FAULTMASK should be 0 on reset, like PRIMASK.
QEMU stores FAULTMASK in the PSTATE F bit, so (as with PRIMASK in the
I bit) we have to clear these to undo the A profile default of 1.

Update the comment accordingly and move it so that it's closer to the
code it's referring to.

Signed-off-by: default avatarMichael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-10-git-send-email-peter.maydell@linaro.org
[PMM: rewrote commit message, moved comments]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent bdd04fc7
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+6 −4
Original line number Diff line number Diff line
@@ -179,15 +179,16 @@ static void arm_cpu_reset(CPUState *s)
    /* SVC mode with interrupts disabled.  */
    env->uncached_cpsr = ARM_CPU_MODE_SVC;
    env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
    /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
     * clear at reset. Initial SP and PC are loaded from ROM.
     */

    if (arm_feature(env, ARM_FEATURE_M)) {
        uint32_t initial_msp; /* Loaded from 0x0 */
        uint32_t initial_pc; /* Loaded from 0x4 */
        uint8_t *rom;

        env->daif &= ~PSTATE_I;
        /* For M profile we store FAULTMASK and PRIMASK in the
         * PSTATE F and I bits; these are both clear at reset.
         */
        env->daif &= ~(PSTATE_I | PSTATE_F);

        /* The reset value of this bit is IMPDEF, but ARM recommends
         * that it resets to 1, so QEMU always does that rather than making
@@ -195,6 +196,7 @@ static void arm_cpu_reset(CPUState *s)
         */
        env->v7m.ccr = R_V7M_CCR_STKALIGN_MASK;

        /* Load the initial SP and PC from the vector table at address 0 */
        rom = rom_ptr(0);
        if (rom) {
            /* Address zero is covered by ROM which hasn't yet been