Commit bdd04fc7 authored by Michael Davidsaver's avatar Michael Davidsaver Committed by Peter Maydell
Browse files

armv7m: Honour CCR.USERSETMPEND 



The CCR.USERSETMPEND bit has to be set to permit unprivileged code to
write to the Software Triggered Interrupt register; honour this bit
rather than letting any code write to the register.

Signed-off-by: default avatarMichael Davidsaver <mdavidsaver@gmail.com>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-9-git-send-email-peter.maydell@linaro.org
[PMM: Tweak commit message, comment, phrasing of condition]
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 7517748e

hw/intc/armv7m_nvic.c

+4 −1
Original line number Diff line number Diff line
@@ -409,7 +409,10 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) 
                      "NVIC: Aux fault status registers unimplemented\n");

        break;

    case 0xf00: /* Software Triggered Interrupt Register */

        if ((value & 0x1ff) < s->num_irq) {

        /* user mode can only write to STIR if CCR.USERSETMPEND permits it */

        if ((value & 0x1ff) < s->num_irq &&

            (arm_current_el(&cpu->env) ||

             (cpu->env.v7m.ccr & R_V7M_CCR_USERSETMPEND_MASK))) {

            gic_set_pending_private(&s->gic, 0, value & 0x1ff);

        }

        break;