Commit 7517748e authored by Peter Maydell's avatar Peter Maydell
Browse files

armv7m: Report no-coprocessor faults correctly 



For v7M attempts to access a nonexistent coprocessor are reported
differently from plain undefined instructions (as UsageFaults of type
NOCP rather than type UNDEFINSTR).  Split them out into a new
EXCP_NOCP so we can report the FSR value correctly.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarAlex Bennée <alex.bennee@linaro.org>
Message-id: 1485285380-10565-8-git-send-email-peter.maydell@linaro.org
parent 81dd9648

linux-user/main.c

+1 −0
Original line number Diff line number Diff line
@@ -573,6 +573,7 @@ void cpu_loop(CPUARMState *env) 


        switch(trapnr) {

        case EXCP_UDEF:

        case EXCP_NOCP:

            {

                TaskState *ts = cs->opaque;

                uint32_t opcode;

target/arm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ 
#define EXCP_VIRQ           14

#define EXCP_VFIQ           15

#define EXCP_SEMIHOST       16   /* semihosting call */

#define EXCP_NOCP           17   /* v7M NOCP UsageFault */



#define ARMV7M_EXCP_RESET   1

#define ARMV7M_EXCP_NMI     2

target/arm/helper.c

+4 −0
Original line number Diff line number Diff line
@@ -6074,6 +6074,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) 
        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

        env->v7m.cfsr |= R_V7M_CFSR_UNDEFINSTR_MASK;

        return;

    case EXCP_NOCP:

        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);

        env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;

        return;

    case EXCP_SWI:

        /* The PC already points to the next instruction.  */

        armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);

target/arm/translate.c

+8 −0
Original line number Diff line number Diff line
@@ -10217,6 +10217,14 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw 
        break;

    case 6: case 7: case 14: case 15:

        /* Coprocessor.  */

        if (arm_dc_feature(s, ARM_FEATURE_M)) {

            /* We don't currently implement M profile FP support,

             * so this entire space should give a NOCP fault.

             */

            gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),

                               default_exception_el(s));

            break;

        }

        if (((insn >> 24) & 3) == 3) {

            /* Translate into the equivalent ARM encoding.  */

            insn = (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 << 28);