Commit dae8fb90 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE reverse within elements 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-9-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent 792a5578

target/arm/helper-sve.h

+14 −0
Original line number Diff line number Diff line
@@ -465,6 +465,20 @@ DEF_HELPER_FLAGS_4(sve_compact_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) 


DEF_HELPER_FLAGS_2(sve_last_active_element, TCG_CALL_NO_RWG, s32, ptr, i32)



DEF_HELPER_FLAGS_4(sve_revb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_revb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_revb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_4(sve_revh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)



DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)

target/arm/sve.decode

+7 −0
Original line number Diff line number Diff line
@@ -456,6 +456,13 @@ CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn 
# SVE copy element from general register to vector (predicated)

CPY_m_r         00000101 .. 101000 101 ... ..... .....          @rd_pg_rn



# SVE reverse within elements

# Note esz >= operation size

REVB            00000101 .. 1001 00 100 ... ..... .....         @rd_pg_rn

REVH            00000101 .. 1001 01 100 ... ..... .....         @rd_pg_rn

REVW            00000101 .. 1001 10 100 ... ..... .....         @rd_pg_rn

RBIT            00000101 .. 1001 11 100 ... ..... .....         @rd_pg_rn



### SVE Predicate Logical Operations Group



# SVE predicate logical operations

target/arm/sve_helper.c

+34 −7
Original line number Diff line number Diff line
@@ -238,6 +238,26 @@ static inline uint64_t expand_pred_s(uint8_t byte) 
    return word[byte & 0x11];

}



/* Swap 16-bit words within a 32-bit word.  */

static inline uint32_t hswap32(uint32_t h)

{

    return rol32(h, 16);

}



/* Swap 16-bit words within a 64-bit word.  */

static inline uint64_t hswap64(uint64_t h)

{

    uint64_t m = 0x0000ffff0000ffffull;

    h = rol64(h, 32);

    return ((h & m) << 16) | ((h >> 16) & m);

}



/* Swap 32-bit words within a 64-bit word.  */

static inline uint64_t wswap64(uint64_t h)

{

    return rol64(h, 32);

}



#define LOGICAL_PPPP(NAME, FUNC) \

void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc)  \

{                                                                         \
@@ -616,6 +636,20 @@ DO_ZPZ(sve_neg_h, uint16_t, H1_2, DO_NEG) 
DO_ZPZ(sve_neg_s, uint32_t, H1_4, DO_NEG)

DO_ZPZ_D(sve_neg_d, uint64_t, DO_NEG)



DO_ZPZ(sve_revb_h, uint16_t, H1_2, bswap16)

DO_ZPZ(sve_revb_s, uint32_t, H1_4, bswap32)

DO_ZPZ_D(sve_revb_d, uint64_t, bswap64)



DO_ZPZ(sve_revh_s, uint32_t, H1_4, hswap32)

DO_ZPZ_D(sve_revh_d, uint64_t, hswap64)



DO_ZPZ_D(sve_revw_d, uint64_t, wswap64)



DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8)

DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16)

DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32)

DO_ZPZ_D(sve_rbit_d, uint64_t, revbit64)



/* Three-operand expander, unpredicated, in which the third operand is "wide".

 */

#define DO_ZZW(NAME, TYPE, TYPEW, H, OP)                       \
@@ -1587,13 +1621,6 @@ void HELPER(sve_rev_b)(void *vd, void *vn, uint32_t desc) 
    }

}



static inline uint64_t hswap64(uint64_t h)

{

    uint64_t m = 0x0000ffff0000ffffull;

    h = rol64(h, 32);

    return ((h & m) << 16) | ((h >> 16) & m);

}



void HELPER(sve_rev_h)(void *vd, void *vn, uint32_t desc)

{

    intptr_t i, j, opr_sz = simd_oprsz(desc);

target/arm/translate-sve.c

+38 −0
Original line number Diff line number Diff line
@@ -2643,6 +2643,44 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) 
    return true;

}



static bool trans_REVB(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    static gen_helper_gvec_3 * const fns[4] = {

        NULL,

        gen_helper_sve_revb_h,

        gen_helper_sve_revb_s,

        gen_helper_sve_revb_d,

    };

    return do_zpz_ool(s, a, fns[a->esz]);

}



static bool trans_REVH(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    static gen_helper_gvec_3 * const fns[4] = {

        NULL,

        NULL,

        gen_helper_sve_revh_s,

        gen_helper_sve_revh_d,

    };

    return do_zpz_ool(s, a, fns[a->esz]);

}



static bool trans_REVW(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL);

}



static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    static gen_helper_gvec_3 * const fns[4] = {

        gen_helper_sve_rbit_b,

        gen_helper_sve_rbit_h,

        gen_helper_sve_rbit_s,

        gen_helper_sve_rbit_d,

    };

    return do_zpz_ool(s, a, fns[a->esz]);

}



/*

 *** SVE Memory - 32-bit Gather and Unsized Contiguous Group

 */