Commit 792a5578 authored by Richard Henderson's avatar Richard Henderson Committed by Peter Maydell
Browse files

target/arm: Implement SVE copy to vector (predicated) 



Reviewed-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Message-id: 20180613015641.5667-8-richard.henderson@linaro.org
Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
parent ef23cb72

target/arm/sve.decode

+6 −0
Original line number Diff line number Diff line
@@ -450,6 +450,12 @@ LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn 
LASTA_r         00000101 .. 10000 0 101 ... ..... .....         @rd_pg_rn

LASTB_r         00000101 .. 10000 1 101 ... ..... .....         @rd_pg_rn



# SVE copy element from SIMD&FP scalar register

CPY_m_v         00000101 .. 100000 100 ... ..... .....          @rd_pg_rn



# SVE copy element from general register to vector (predicated)

CPY_m_r         00000101 .. 101000 101 ... ..... .....          @rd_pg_rn



### SVE Predicate Logical Operations Group



# SVE predicate logical operations

target/arm/translate-sve.c

+19 −0
Original line number Diff line number Diff line
@@ -2624,6 +2624,25 @@ static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn) 
    return do_last_general(s, a, true);

}



static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    if (sve_access_check(s)) {

        do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn));

    }

    return true;

}



static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)

{

    if (sve_access_check(s)) {

        int ofs = vec_reg_offset(s, a->rn, 0, a->esz);

        TCGv_i64 t = load_esz(cpu_env, ofs, a->esz);

        do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t);

        tcg_temp_free_i64(t);

    }

    return true;

}



/*

 *** SVE Memory - 32-bit Gather and Unsized Contiguous Group

 */