Commit d8ed887b authored by Andreas Färber's avatar Andreas Färber
Browse files

exec: Pass CPUState to cpu_reset_interrupt() 



Move it to qom/cpu.c to avoid build failures depending on include order
of cpu-qom.h and exec/cpu-all.h.

Change opaques of various ..._irq_handler() functions to the
appropriate CPU type to facilitate using cpu_reset_interrupt().

Fix Coding Style issues while at it (missing braces, indentation).

Signed-off-by: default avatarAndreas Färber <afaerber@suse.de>
parent 259186a7

exec.c

+0 −7
Original line number Diff line number Diff line
@@ -492,13 +492,6 @@ void cpu_single_step(CPUArchState *env, int enabled) 
#endif

}



void cpu_reset_interrupt(CPUArchState *env, int mask)

{

    CPUState *cpu = ENV_GET_CPU(env);



    cpu->interrupt_request &= ~mask;

}



void cpu_exit(CPUArchState *env)

{

    CPUState *cpu = ENV_GET_CPU(env);

hw/alpha_typhoon.c

+5 −3
Original line number Diff line number Diff line
@@ -63,10 +63,11 @@ static void cpu_irq_change(AlphaCPU *cpu, uint64_t req) 
    /* If there are any non-masked interrupts, tell the cpu.  */

    if (cpu != NULL) {

        CPUAlphaState *env = &cpu->env;

        CPUState *cs = CPU(cpu);

        if (req) {

            cpu_interrupt(env, CPU_INTERRUPT_HARD);

        } else {

            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);

            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

        }

    }

}
@@ -359,16 +360,17 @@ static void cchip_write(void *opaque, hwaddr addr, 
                AlphaCPU *cpu = s->cchip.cpu[i];

                if (cpu != NULL) {

                    CPUAlphaState *env = &cpu->env;

                    CPUState *cs = CPU(cpu);

                    /* IPI can be either cleared or set by the write.  */

                    if (newval & (1 << (i + 8))) {

                        cpu_interrupt(env, CPU_INTERRUPT_SMP);

                    } else {

                        cpu_reset_interrupt(env, CPU_INTERRUPT_SMP);

                        cpu_reset_interrupt(cs, CPU_INTERRUPT_SMP);

                    }



                    /* ITI can only be cleared by the write.  */

                    if ((newval & (1 << (i + 4))) == 0) {

                        cpu_reset_interrupt(env, CPU_INTERRUPT_TIMER);

                        cpu_reset_interrupt(cs, CPU_INTERRUPT_TIMER);

                    }

                }

            }

hw/apic.c

+2 −2
Original line number Diff line number Diff line
@@ -187,7 +187,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level) 
            reset_bit(s->irr, lvt & 0xff);

            /* fall through */

        case APIC_DM_EXTINT:

            cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);

            cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_HARD);

            break;

        }

    }
@@ -485,7 +485,7 @@ void apic_sipi(DeviceState *d) 
{

    APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);



    cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);

    cpu_reset_interrupt(CPU(s->cpu), CPU_INTERRUPT_SIPI);



    if (!s->wait_for_sipi)

        return;

hw/arm/pic_cpu.c

+9 −6
Original line number Diff line number Diff line
@@ -16,19 +16,22 @@ static void arm_pic_cpu_handler(void *opaque, int irq, int level) 
{

    ARMCPU *cpu = opaque;

    CPUARMState *env = &cpu->env;

    CPUState *cs = CPU(cpu);



    switch (irq) {

    case ARM_PIC_CPU_IRQ:

        if (level)

        if (level) {

            cpu_interrupt(env, CPU_INTERRUPT_HARD);

        else

            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);

        } else {

            cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);

        }

        break;

    case ARM_PIC_CPU_FIQ:

        if (level)

        if (level) {

            cpu_interrupt(env, CPU_INTERRUPT_FIQ);

        else

            cpu_reset_interrupt(env, CPU_INTERRUPT_FIQ);

        } else {

            cpu_reset_interrupt(cs, CPU_INTERRUPT_FIQ);

        }

        break;

    default:

        hw_error("arm_pic_cpu_handler: Bad interrupt line %d\n", irq);

hw/arm/pxa2xx_pic.c

+2 −2
Original line number Diff line number Diff line
@@ -62,13 +62,13 @@ static void pxa2xx_pic_update(void *opaque) 
    if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1])) {

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);

    } else {

        cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_FIQ);

        cpu_reset_interrupt(cpu, CPU_INTERRUPT_FIQ);

    }



    if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1])) {

        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);

    } else {

        cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);

        cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD);

    }

}