Commit d87576e3 authored by Peter Maydell's avatar Peter Maydell
Browse files

arm_gicv3: Fix broken logic in ELRSR calculation 

Fix a broken expression in the calculation of ELRSR
register bits: instead of "(lr & ICH_LR_EL2_HW) == 1"
we want to check for != 0, because the HW bit is not
bit 0 so a test for == 1 is always false.

Fixes: https://bugs.launchpad.net/bugs/1658506



Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarThomas Huth <thuth@redhat.com>
Message-id: 1485255993-6322-1-git-send-email-peter.maydell@linaro.org
parent e62694a0

hw/intc/arm_gicv3_cpuif.c

+1 −1
Original line number Diff line number Diff line
@@ -2430,7 +2430,7 @@ static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri) 
        uint64_t lr = cs->ich_lr_el2[i];



        if ((lr & ICH_LR_EL2_STATE_MASK) == 0 &&

            ((lr & ICH_LR_EL2_HW) == 1 || (lr & ICH_LR_EL2_EOI) == 0)) {

            ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) {

            value |= (1 << i);

        }

    }