Commit d2f004c3 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias
Browse files

target-microblaze: mmu: Prepare for 64-bit addresses 



Prepare for 64-bit addresses.
This makes no functional difference as the upper parts of
the 64-bit addresses are not yet reachable.

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent 96716533

target/microblaze/mmu.c

+7 −7
Original line number Diff line number Diff line
@@ -81,16 +81,16 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, 
{

    unsigned int i, hit = 0;

    unsigned int tlb_ex = 0, tlb_wr = 0, tlb_zsel;

    unsigned int tlb_size;

    uint32_t tlb_tag, tlb_rpn, mask, t0;

    uint64_t tlb_tag, tlb_rpn, mask;

    uint32_t tlb_size, t0;



    lu->err = ERR_MISS;

    for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) {

        uint32_t t, d;

        uint64_t t, d;



        /* Lookup and decode.  */

        t = mmu->rams[RAM_TAG][i];

        D(qemu_log("TLB %d valid=%d\n", i, t & TLB_VALID));

        D(qemu_log("TLB %d valid=%" PRId64 "\n", i, t & TLB_VALID));

        if (t & TLB_VALID) {

            tlb_size = tlb_decode_size((t & TLB_PAGESZ_MASK) >> 7);

            if (tlb_size < TARGET_PAGE_SIZE) {
@@ -98,10 +98,10 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, 
                abort();

            }



            mask = ~(tlb_size - 1);

            mask = ~((uint64_t)tlb_size - 1);

            tlb_tag = t & TLB_EPN_MASK;

            if ((vaddr & mask) != (tlb_tag & mask)) {

                D(qemu_log("TLB %d vaddr=%x != tag=%x\n",

                D(qemu_log("TLB %d vaddr=%" PRIx64 " != tag=%" PRIx64 "\n",

                           i, vaddr & mask, tlb_tag & mask));

                continue;

            }
@@ -173,7 +173,7 @@ unsigned int mmu_translate(struct microblaze_mmu *mmu, 
        }

    }

done:

    D(qemu_log("MMU vaddr=%x rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",

    D(qemu_log("MMU vaddr=%" PRIx64 " rw=%d tlb_wr=%d tlb_ex=%d hit=%d\n",

              vaddr, rw, tlb_wr, tlb_ex, hit));

    return hit;

}

target/microblaze/mmu.h

+3 −3
Original line number Diff line number Diff line
@@ -28,7 +28,7 @@ 
#define RAM_TAG      0



/* Tag portion */

#define TLB_EPN_MASK          0xFFFFFC00 /* Effective Page Number */

#define TLB_EPN_MASK          MAKE_64BIT_MASK(10, 64 - 10)

#define TLB_PAGESZ_MASK       0x00000380

#define TLB_PAGESZ(x)         (((x) & 0x7) << 7)

#define PAGESZ_1K             0
@@ -42,7 +42,7 @@ 
#define TLB_VALID             0x00000040 /* Entry is valid */



/* Data portion */

#define TLB_RPN_MASK          0xFFFFFC00 /* Real Page Number */

#define TLB_RPN_MASK          MAKE_64BIT_MASK(10, 64 - 10)

#define TLB_PERM_MASK         0x00000300

#define TLB_EX                0x00000200 /* Instruction execution allowed */

#define TLB_WR                0x00000100 /* Writes permitted */
@@ -63,7 +63,7 @@ 
struct microblaze_mmu

{

    /* Data and tag brams.  */

    uint32_t rams[2][TLB_ENTRIES];

    uint64_t rams[2][TLB_ENTRIES];

    /* We keep a separate ram for the tids to avoid the 48 bit tag width.  */

    uint8_t tids[TLB_ENTRIES];

    /* Control flops.  */