Commit 96716533 authored by Edgar E. Iglesias's avatar Edgar E. Iglesias
Browse files

target-microblaze: mmu: Remove unused register state 



Add explicit handling for MMU_R_TLBX and log accesses to
invalid MMU registers. We can now remove the state for
all regs but PID, ZPR and TLBX (0 - 2).

Reviewed-by: default avatarRichard Henderson <richard.henderson@linaro.org>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
parent a2207b59

target/microblaze/mmu.c

+5 −2
Original line number Diff line number Diff line
@@ -211,11 +211,14 @@ uint32_t mmu_read(CPUMBState *env, uint32_t rn) 
            }

            r = env->mmu.regs[rn];

            break;

        case MMU_R_TLBX:

            r = env->mmu.regs[rn];

            break;

        case MMU_R_TLBSX:

            qemu_log_mask(LOG_GUEST_ERROR, "TLBSX is write-only.\n");

            break;

        default:

            r = env->mmu.regs[rn];

            qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);

            break;

    }

    D(qemu_log("%s rn=%d=%x\n", __func__, rn, r));
@@ -298,7 +301,7 @@ void mmu_write(CPUMBState *env, uint32_t rn, uint32_t v) 
            break;

        }

        default:

            env->mmu.regs[rn] = v;

            qemu_log_mask(LOG_GUEST_ERROR, "Invalid MMU register %d.\n", rn);

            break;

   }

}

target/microblaze/mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ struct microblaze_mmu 
    /* We keep a separate ram for the tids to avoid the 48 bit tag width.  */

    uint8_t tids[TLB_ENTRIES];

    /* Control flops.  */

    uint32_t regs[8];

    uint32_t regs[3];



    int c_mmu;

    int c_mmu_tlb_access;