Commit cea66e91 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Implement AArch64 TLBI operations on IPAs 



Implement the AArch64 TLBI operations which take an intermediate
physical address and invalidate stage 2 translations.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1439548879-1972-7-git-send-email-peter.maydell@linaro.org
parent 43efaa33

target-arm/helper.c

+55 −0
Original line number Diff line number Diff line
@@ -2709,6 +2709,45 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    }

}



static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                    uint64_t value)

{

    /* Invalidate by IPA. This has to invalidate any structures that

     * contain only stage 2 translation information, but does not need

     * to apply to structures that contain combined stage 1 and stage 2

     * translation information.

     * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.

     */

    ARMCPU *cpu = arm_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    uint64_t pageaddr;



    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

        return;

    }



    pageaddr = sextract64(value << 12, 0, 48);



    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);

}



static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                      uint64_t value)

{

    CPUState *other_cs;

    uint64_t pageaddr;



    if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {

        return;

    }



    pageaddr = sextract64(value << 12, 0, 48);



    CPU_FOREACH(other_cs) {

        tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);

    }

}



static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)

{

    /* We don't implement EL2, so the only control on DC ZVA is the
@@ -2889,6 +2928,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
      .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,

      .access = PL1_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_vae1_write },

    { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_ipas2e1is_write },

    { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_ipas2e1is_write },

    { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,

      .access = PL2_W, .type = ARM_CP_NO_RAW,
@@ -2897,6 +2944,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_alle1is_write },

    { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_ipas2e1_write },

    { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_ipas2e1_write },

    { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,

      .access = PL2_W, .type = ARM_CP_NO_RAW,