Commit 43efaa33 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Implement missing EL3 TLB invalidate operations 



Implement the remaining stage 1 TLB invalidate operations
visible from EL3.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarEdgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1439548879-1972-6-git-send-email-peter.maydell@linaro.org
parent 2bfb9d75

target-arm/helper.c

+76 −0
Original line number Diff line number Diff line
@@ -2567,6 +2567,15 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);

}



static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                  uint64_t value)

{

    ARMCPU *cpu = arm_env_get_cpu(env);

    CPUState *cs = CPU(cpu);



    tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);

}



static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                    uint64_t value)

{
@@ -2601,6 +2610,16 @@ static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    }

}



static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                    uint64_t value)

{

    CPUState *other_cs;



    CPU_FOREACH(other_cs) {

        tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);

    }

}



static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                 uint64_t value)

{
@@ -2636,6 +2655,20 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);

}



static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                 uint64_t value)

{

    /* Invalidate by VA, EL3

     * Currently handles both VAE3 and VALE3, since we don't support

     * flush-last-level-only.

     */

    ARMCPU *cpu = arm_env_get_cpu(env);

    CPUState *cs = CPU(cpu);

    uint64_t pageaddr = sextract64(value << 12, 0, 56);



    tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);

}



static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                   uint64_t value)

{
@@ -2665,6 +2698,17 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, 
    }

}



static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,

                                   uint64_t value)

{

    CPUState *other_cs;

    uint64_t pageaddr = sextract64(value << 12, 0, 56);



    CPU_FOREACH(other_cs) {

        tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);

    }

}



static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)

{

    /* We don't implement EL2, so the only control on DC ZVA is the
@@ -2849,10 +2893,18 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_alle1is_write },

    { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_alle1is_write },

    { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_alle1_write },

    { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,

      .access = PL2_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_alle1is_write },

#ifndef CONFIG_USER_ONLY

    /* 64 bit address translation operations */

    { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
@@ -3317,6 +3369,30 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { 
      .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,

      .access = PL3_RW, .type = ARM_CP_CONST,

      .resetvalue = 0 },

    { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,

      .access = PL3_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_alle3is_write },

    { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,

      .access = PL3_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_vae3is_write },

    { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,

      .access = PL3_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_vae3is_write },

    { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,

      .access = PL3_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_alle3_write },

    { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,

      .access = PL3_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_vae3_write },

    { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,

      .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,

      .access = PL3_W, .type = ARM_CP_NO_RAW,

      .writefn = tlbi_aa64_vae3_write },

    REGINFO_SENTINEL

};