Commit cdc46fab authored by Leon Alrae's avatar Leon Alrae
Browse files

target-mips: enable 10-bit ASIDs in I6400 CPU 



Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent a0c80608

target-mips/translate_init.c

+1 −1
Original line number Diff line number Diff line
@@ -685,7 +685,7 @@ static const mips_def_t mips_defs[] = 
                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |

                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),

        .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |

                       (0xfc << CP0C4_KScrExist),

                       (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist),

        .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) |

                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),

        .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |