Commit a0c80608 authored by Paul Burton's avatar Paul Burton Committed by Leon Alrae
Browse files

target-mips: support CP0.Config4.AE bit 



The read-only Config4.AE bit set denotes extended 10 bits ASID.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent 2d72e7b0

target-mips/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -468,6 +468,7 @@ struct CPUMIPSState { 
    int32_t CP0_Config4_rw_bitmask;

#define CP0C4_M    31

#define CP0C4_IE   29

#define CP0C4_AE   28

#define CP0C4_KScrExist 16

#define CP0C4_MMUExtDef 14

#define CP0C4_FTLBPageSize 8

target-mips/translate.c

+2 −1
Original line number Diff line number Diff line
@@ -20302,7 +20302,8 @@ void cpu_state_reset(CPUMIPSState *env) 
    if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) {

        env->CP0_CMGCRBase = 0x1fbf8000 >> 4;

    }

    env->CP0_EntryHi_ASID_mask = 0xff;

    env->CP0_EntryHi_ASID_mask = (env->CP0_Config4 & (1 << CP0C4_AE)) ?

                                 0x3ff : 0xff;

    env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);

    /* vectored interrupts not implemented, timer on int 7,

       no performance counters. */