Commit 2d72e7b0 authored by Paul Burton's avatar Paul Burton Committed by Leon Alrae
Browse files

target-mips: change ASID type to hold more than 8 bits 



ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.

Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Signed-off-by: default avatarLeon Alrae <leon.alrae@imgtec.com>
parent 6ec98bd7

target-mips/cpu.h

+1 −1
Original line number Diff line number Diff line
@@ -19,7 +19,7 @@ typedef struct r4k_tlb_t r4k_tlb_t; 
struct r4k_tlb_t {

    target_ulong VPN;

    uint32_t PageMask;

    uint8_t ASID;

    uint16_t ASID;

    unsigned int G:1;

    unsigned int C0:3;

    unsigned int C1:3;

target-mips/helper.c

+2 −2
Original line number Diff line number Diff line
@@ -67,7 +67,7 @@ int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot, 
int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,

                     target_ulong address, int rw, int access_type)

{

    uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;

    uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;

    int i;



    for (i = 0; i < env->tlb->tlb_in_use; i++) {
@@ -898,7 +898,7 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) 
    r4k_tlb_t *tlb;

    target_ulong addr;

    target_ulong end;

    uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;

    uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;

    target_ulong mask;



    tlb = &env->tlb->mmu.r4k.tlb[idx];

target-mips/machine.c

+5 −5
Original line number Diff line number Diff line
@@ -132,7 +132,7 @@ static int get_tlb(QEMUFile *f, void *pv, size_t size) 


    qemu_get_betls(f, &v->VPN);

    qemu_get_be32s(f, &v->PageMask);

    qemu_get_8s(f, &v->ASID);

    qemu_get_be16s(f, &v->ASID);

    qemu_get_be16s(f, &flags);

    v->G = (flags >> 10) & 1;

    v->C0 = (flags >> 7) & 3;
@@ -156,7 +156,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) 
{

    r4k_tlb_t *v = pv;



    uint8_t asid = v->ASID;

    uint16_t asid = v->ASID;

    uint16_t flags = ((v->EHINV << 15) |

                      (v->RI1 << 14) |

                      (v->RI0 << 13) |
@@ -172,7 +172,7 @@ static void put_tlb(QEMUFile *f, void *pv, size_t size) 


    qemu_put_betls(f, &v->VPN);

    qemu_put_be32s(f, &v->PageMask);

    qemu_put_8s(f, &asid);

    qemu_put_be16s(f, &asid);

    qemu_put_be16s(f, &flags);

    qemu_put_be64s(f, &v->PFN[0]);

    qemu_put_be64s(f, &v->PFN[1]);
@@ -192,8 +192,8 @@ const VMStateInfo vmstate_info_tlb = { 


const VMStateDescription vmstate_tlb = {

    .name = "cpu/tlb",

    .version_id = 1,

    .minimum_version_id = 1,

    .version_id = 2,

    .minimum_version_id = 2,

    .fields = (VMStateField[]) {

        VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext),

        VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext),

target-mips/op_helper.c

+4 −4
Original line number Diff line number Diff line
@@ -2013,7 +2013,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env) 
{

    int idx;

    r4k_tlb_t *tlb;

    uint8_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;

    uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;



    for (idx = 0; idx < env->tlb->nb_tlb; idx++) {

        tlb = &env->tlb->mmu.r4k.tlb[idx];
@@ -2039,7 +2039,7 @@ void r4k_helper_tlbwi(CPUMIPSState *env) 
    r4k_tlb_t *tlb;

    int idx;

    target_ulong VPN;

    uint8_t ASID;

    uint16_t ASID;

    bool G, V0, D0, V1, D1;



    idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
@@ -2081,7 +2081,7 @@ void r4k_helper_tlbp(CPUMIPSState *env) 
    target_ulong mask;

    target_ulong tag;

    target_ulong VPN;

    uint8_t ASID;

    uint16_t ASID;

    int i;



    ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
@@ -2136,7 +2136,7 @@ static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) 
void r4k_helper_tlbr(CPUMIPSState *env)

{

    r4k_tlb_t *tlb;

    uint8_t ASID;

    uint16_t ASID;

    int idx;



    ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;