Commit cd4da631 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Implement AArch64 MIDR_EL1 



Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
parent 0eef9d98

target-arm/helper.c

+3 −0
Original line number Diff line number Diff line
@@ -1720,6 +1720,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) 
              .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,

              .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),

              .type = ARM_CP_OVERRIDE },

            { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64,

              .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0,

              .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST },

            { .name = "CTR",

              .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,

              .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },