Commit 0eef9d98 authored by Peter Maydell's avatar Peter Maydell
Browse files

target-arm: Implement AArch64 CurrentEL sysreg 



Implement the CurrentEL sysreg.

Signed-off-by: default avatarPeter Maydell <peter.maydell@linaro.org>
Reviewed-by: default avatarPeter Crosthwaite <peter.crosthwaite@xilinx.com>
parent 7da845b0

target-arm/cpu.h

+2 −1
Original line number Diff line number Diff line
@@ -731,7 +731,8 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid) 
#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))

#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))

#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))

#define ARM_LAST_SPECIAL ARM_CP_NZCV

#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))

#define ARM_LAST_SPECIAL ARM_CP_CURRENTEL

/* Used only as a terminator for ARMCPRegInfo lists */

#define ARM_CP_SENTINEL 0xffff

/* Mask of only the flag bits in a type field */

target-arm/helper.c

+3 −0
Original line number Diff line number Diff line
@@ -1533,6 +1533,9 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { 
      .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,

      .access = PL0_R, .type = ARM_CP_CONST,

      .resetvalue = 0x10 },

    { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,

      .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,

      .access = PL1_R, .type = ARM_CP_CURRENTEL },

    REGINFO_SENTINEL

};

target-arm/translate-a64.c

+7 −0
Original line number Diff line number Diff line
@@ -1231,6 +1231,13 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, 
            gen_set_nzcv(tcg_rt);

        }

        return;

    case ARM_CP_CURRENTEL:

        /* Reads as current EL value from pstate, which is

         * guaranteed to be constant by the tb flags.

         */

        tcg_rt = cpu_reg(s, rt);

        tcg_gen_movi_i64(tcg_rt, s->current_pl << 2);

        return;

    default:

        break;

    }