Commit cc411260 authored by Alistair Francis's avatar Alistair Francis
Browse files

riscv/opentitan: Connect the UART device 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarBin Meng <bin.meng@windriver.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
parent b9fc5135

hw/riscv/opentitan.c

+23 −2
Original line number Diff line number Diff line
@@ -97,6 +97,8 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) 
    object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);



    object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);



    object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);

}



static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -133,8 +135,27 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 
    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base);



    create_unimplemented_device("riscv.lowrisc.ibex.uart",

        memmap[IBEX_UART].base, memmap[IBEX_UART].size);

    /* UART */

    qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));

    sysbus_realize(SYS_BUS_DEVICE(&s->uart), &err);

    if (err != NULL) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_UART].base);

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),

                       0, qdev_get_gpio_in(DEVICE(&s->plic),

                       IBEX_UART_TX_WATERMARK_IRQ));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),

                       1, qdev_get_gpio_in(DEVICE(&s->plic),

                       IBEX_UART_RX_WATERMARK_IRQ));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),

                       2, qdev_get_gpio_in(DEVICE(&s->plic),

                       IBEX_UART_TX_EMPTY_IRQ));

    sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),

                       3, qdev_get_gpio_in(DEVICE(&s->plic),

                       IBEX_UART_RX_OVERFLOW_IRQ));



    create_unimplemented_device("riscv.lowrisc.ibex.gpio",

        memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);

    create_unimplemented_device("riscv.lowrisc.ibex.spi",

include/hw/riscv/opentitan.h

+13 −0
Original line number Diff line number Diff line
@@ -21,6 +21,7 @@ 


#include "hw/riscv/riscv_hart.h"

#include "hw/intc/ibex_plic.h"

#include "hw/char/ibex_uart.h"



#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"

#define RISCV_IBEX_SOC(obj) \
@@ -33,6 +34,7 @@ typedef struct LowRISCIbexSoCState { 
    /*< public >*/

    RISCVHartArrayState cpus;

    IbexPlicState plic;

    IbexUartState uart;



    MemoryRegion flash_mem;

    MemoryRegion rom;
@@ -68,4 +70,15 @@ enum { 
    IBEX_PADCTRL,

};



enum {

    IBEX_UART_RX_PARITY_ERR_IRQ = 0x28,

    IBEX_UART_RX_TIMEOUT_IRQ = 0x27,

    IBEX_UART_RX_BREAK_ERR_IRQ = 0x26,

    IBEX_UART_RX_FRAME_ERR_IRQ = 0x25,

    IBEX_UART_RX_OVERFLOW_IRQ = 0x24,

    IBEX_UART_TX_EMPTY_IRQ = 0x23,

    IBEX_UART_RX_WATERMARK_IRQ = 0x22,

    IBEX_UART_TX_WATERMARK_IRQ = 0x21,

};



#endif