Commit b9fc5135 authored by Alistair Francis's avatar Alistair Francis
Browse files

riscv/opentitan: Connect the PLIC device 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarBin Meng <bin.meng@windriver.com>
Reviewed-by: default avatarPhilippe Mathieu-Daudé <f4bug@amsat.org>
parent 879f60f0

hw/riscv/opentitan.c

+12 −2
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "hw/riscv/boot.h"

#include "exec/address-spaces.h"

#include "qemu/units.h"

#include "sysemu/sysemu.h"



static const struct MemmapEntry {

    hwaddr base;
@@ -94,6 +95,8 @@ static void riscv_lowrisc_ibex_soc_init(Object *obj) 
    LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);



    object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);



    object_initialize_child(obj, "plic", &s->plic, TYPE_IBEX_PLIC);

}



static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
@@ -102,6 +105,7 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 
    MachineState *ms = MACHINE(qdev_get_machine());

    LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);

    MemoryRegion *sys_mem = get_system_memory();

    Error *err = NULL;



    object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",

                            &error_abort);
@@ -121,6 +125,14 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 
    memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,

                                &s->flash_mem);



    /* PLIC */

    sysbus_realize(SYS_BUS_DEVICE(&s->plic), &err);

    if (err != NULL) {

        error_propagate(errp, err);

        return;

    }

    sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base);



    create_unimplemented_device("riscv.lowrisc.ibex.uart",

        memmap[IBEX_UART].base, memmap[IBEX_UART].size);

    create_unimplemented_device("riscv.lowrisc.ibex.gpio",
@@ -141,8 +153,6 @@ static void riscv_lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) 
        memmap[IBEX_AES].base, memmap[IBEX_AES].size);

    create_unimplemented_device("riscv.lowrisc.ibex.hmac",

        memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);

    create_unimplemented_device("riscv.lowrisc.ibex.plic",

        memmap[IBEX_PLIC].base, memmap[IBEX_PLIC].size);

    create_unimplemented_device("riscv.lowrisc.ibex.pinmux",

        memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);

    create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",

include/hw/riscv/opentitan.h

+3 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#define HW_OPENTITAN_H



#include "hw/riscv/riscv_hart.h"

#include "hw/intc/ibex_plic.h"



#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"

#define RISCV_IBEX_SOC(obj) \
@@ -31,6 +32,8 @@ typedef struct LowRISCIbexSoCState { 


    /*< public >*/

    RISCVHartArrayState cpus;

    IbexPlicState plic;



    MemoryRegion flash_mem;

    MemoryRegion rom;

} LowRISCIbexSoCState;