Unverified Commit c9eefe05 authored by Alistair Francis's avatar Alistair Francis Committed by Palmer Dabbelt
Browse files

target/riscv: Allow enabling the Hypervisor extension 



Signed-off-by: default avatarAlistair Francis <alistair.francis@wdc.com>
Reviewed-by: default avatarPalmer Dabbelt <palmer@sifive.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent e44b50b5

target/riscv/cpu.c

+5 −0
Original line number Diff line number Diff line
@@ -453,6 +453,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) 
        if (cpu->cfg.ext_u) {

            target_misa |= RVU;

        }

        if (cpu->cfg.ext_h) {

            target_misa |= RVH;

        }



        set_misa(env, RVXLEN | target_misa);

    }
@@ -488,6 +491,8 @@ static Property riscv_cpu_properties[] = { 
    DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),

    DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),

    DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),

    /* This is experimental so mark with 'x-' */

    DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),

    DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),

    DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),

    DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),

target/riscv/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -258,6 +258,7 @@ typedef struct RISCVCPU { 
        bool ext_c;

        bool ext_s;

        bool ext_u;

        bool ext_h;

        bool ext_counters;

        bool ext_ifencei;

        bool ext_icsr;