Commit c7efab4f authored by Richard Henderson's avatar Richard Henderson
Browse files

target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init 



These registers are read-only and implementation specific.
Initiailize VR for the first time; take the OR1200 values
from the verilog source.

Note that moving fields within CPUOpenRISCState does not
affect migration.

Reviewed-by: default avatarStafford Horne <shorne@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent b72e3ff6

target/openrisc/cpu.c

+16 −7
Original line number Diff line number Diff line
@@ -56,13 +56,6 @@ static void openrisc_cpu_reset(CPUState *s) 
    cpu->env.lock_addr = -1;

    s->exception_index = -1;



    cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |

                   UPR_PMP;

    cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))

                      | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));

    cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))

                      | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));



#ifndef CONFIG_USER_ONLY

    cpu->env.picmr = 0x00000000;

    cpu->env.picsr = 0x00000000;
@@ -117,15 +110,31 @@ static void or1200_initfn(Object *obj) 
{

    OpenRISCCPU *cpu = OPENRISC_CPU(obj);



    cpu->env.vr = 0x13000008;

    cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;

    cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |

                       CPUCFGR_EVBARP;



    /* 1Way, TLB_SIZE entries.  */

    cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))

                      | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));

    cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))

                      | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));

}



static void openrisc_any_initfn(Object *obj)

{

    OpenRISCCPU *cpu = OPENRISC_CPU(obj);



    cpu->env.vr = 0x13000000;

    cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;

    cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_EVBARP;



    /* 1Way, TLB_SIZE entries.  */

    cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))

                      | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));

    cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))

                      | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));

}



static void openrisc_cpu_class_init(ObjectClass *oc, void *data)

target/openrisc/cpu.h

+4 −4
Original line number Diff line number Diff line
@@ -260,10 +260,6 @@ typedef struct CPUOpenRISCState { 
    target_ulong sr_cy;       /* the SR_CY bit, values 0, 1.  */

    target_long  sr_ov;       /* the SR_OV bit (in the sign bit only) */

    uint32_t sr;              /* Supervisor register, without SR_{F,CY,OV} */

    uint32_t vr;              /* Version register */

    uint32_t upr;             /* Unit presence register */

    uint32_t dmmucfgr;        /* DMMU configure register */

    uint32_t immucfgr;        /* IMMU configure register */

    uint32_t esr;             /* Exception supervisor register */

    uint32_t evbar;           /* Exception vector base address register */

    uint32_t pmr;             /* Power Management Register */
@@ -283,7 +279,11 @@ typedef struct CPUOpenRISCState { 
    struct {} end_reset_fields;



    /* Fields from here on are preserved across CPU reset. */

    uint32_t vr;              /* Version register */

    uint32_t upr;             /* Unit presence register */

    uint32_t cpucfgr;         /* CPU configure register */

    uint32_t dmmucfgr;        /* DMMU configure register */

    uint32_t immucfgr;        /* IMMU configure register */



#ifndef CONFIG_USER_ONLY

    QEMUTimer *timer;

target/openrisc/sys_helper.c

+2 −2
Original line number Diff line number Diff line
@@ -199,13 +199,13 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 
        return env->vr;



    case TO_SPR(0, 1): /* UPR */

        return env->upr;    /* TT, DM, IM, UP present */

        return env->upr;



    case TO_SPR(0, 2): /* CPUCFGR */

        return env->cpucfgr;



    case TO_SPR(0, 3): /* DMMUCFGR */

        return env->dmmucfgr;    /* 1Way, 64 entries */

        return env->dmmucfgr;



    case TO_SPR(0, 4): /* IMMUCFGR */

        return env->immucfgr;