Commit b72e3ff6 authored by Richard Henderson's avatar Richard Henderson
Browse files

target/openrisc: Make VR and PPC read-only 



These SPRs are read-only.  The writes can simply be ignored,
as we already do for other read-only (or missing) registers.
There is no reason to mask the value in env->vr.

Reviewed-by: default avatarStafford Horne <shorne@gmail.com>
Signed-off-by: default avatarRichard Henderson <richard.henderson@linaro.org>
parent d29f4368

target/openrisc/cpu.h

+0 −3
Original line number Diff line number Diff line
@@ -68,9 +68,6 @@ enum { 
                                      (reg) |= ((v & 0x1f) << 2);\

                                  } while (0)



/* Version Register */

#define SPR_VR 0xFFFF003F



/* Interrupt */

#define NR_IRQS  32

target/openrisc/sys_helper.c

+1 −9
Original line number Diff line number Diff line
@@ -39,10 +39,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 
    int idx;



    switch (spr) {

    case TO_SPR(0, 0): /* VR */

        env->vr = rb;

        break;



    case TO_SPR(0, 11): /* EVBAR */

        env->evbar = rb;

        break;
@@ -62,10 +58,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 
        cpu_set_sr(env, rb);

        break;



    case TO_SPR(0, 18): /* PPC */

        env->ppc = rb;

        break;



    case TO_SPR(0, 32): /* EPCR */

        env->epcr = rb;

        break;
@@ -204,7 +196,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 


    switch (spr) {

    case TO_SPR(0, 0): /* VR */

        return env->vr & SPR_VR;

        return env->vr;



    case TO_SPR(0, 1): /* UPR */

        return env->upr;    /* TT, DM, IM, UP present */